Area efficient and high performance approximate multiplier design
Lad, Pinal Bharatbhai
MetadataShow full item record
FPGA can provide an efficient way of approximation due to their reprogrammable structure in contrast to ASIC based approximations. The work presents an optimized approximation methodology for multiplier design which utilizes FPGA architecture based designing concept for introducing approximations. This FPGA based approximation approach provides efficient area utilization and higher performance with high accuracy compared to ASIC based approximate multiplier designs. Approximate multipliers are designed on Xilinx Vivado tool, verified on xsim (Xilinx Simulator) and implemented on Artix 7 AC701 FPGA board. For board level implementation of proposed design, virtual input and output core is used to control and monitor inputs and product output interactively for an approximate multiplier 8x8 design running on Artix 7 AC701 FPGA board to overcome limitation of available on-board hardware resources.
- M Tech Dissertations