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dc.contributor.advisorAgrawal, Yash
dc.contributor.advisorChowdhury, Prohor
dc.contributor.authorJain, Jiket
dc.date.accessioned2020-09-14T07:48:57Z
dc.date.available2020-09-14T07:48:57Z
dc.date.issued2019
dc.identifier.citationJain, Jiket (2019). Study of transactional synchronization extensions (TSX) feature in x86 processor architecture. Dhirubhai Ambani Institute of Information and Communication Technology, 16p. (Acc.No: T00791)
dc.identifier.urihttp://drsr.daiict.ac.in//handle/123456789/871
dc.description.abstractImproving performance has always been at the center of a new CPU design. Simultaneous Multi-Threading is one of the ways to achieve better performance in terms of CPU utilization. In case of Multi-Threading, threads share data and because of which serialization is needed to fulfill synchronization and consistency of shared data between two threads. Such static serialization may be unnecessary and hence Transactional Synchronization Extension (TSX) provides an optimistic approach to do serialization dynamically when needed. A study of TSX is presented. In addition to a brief description of TSX the report presents the flow of verification and possible ways to verify the complex TSX feature. The results itself provides a proof of complexity of the feature in terms of number of CPU cycles simulated to verify it with respect to only Load Store unit. Further, the report suggests possible improvements over different existing architectures and how the feature verification can be improved.
dc.publisherDhirubhai Ambani Institute of Information and Communication Technology
dc.subjectSimultaneous multi threading
dc.subjecttransactional synchrinization extension
dc.subjectCPU design
dc.classification.ddc005.74 JAI
dc.titleStudy of transactional synchronization extensions (TSX) feature in x86 processor architecture
dc.typeDissertation
dc.degreeM.Tech
dc.student.id201711036
dc.accession.numberT00791


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