Emerging On-Chip interconnects for futuristic integrated circuit design

Abstract

Performance of VLSI technology is strongly influenced by interconnect delay. Scaling of ICs leads to many signal integrity issues. The demand for high speed, low power and compact chip size have led on-chip interconnects an interesting research area. Subsequent miniaturization in VLSI technology has led performance of interconnect dominate over device. Currently, copper (Cu) is facing several limitations with technology scaling down. A dire requirement to replace the Cu interconnects has arrived. Due to these limitations, the overall performance of Cu interconnect has been affected. Future interconnects materials like allotropes of carbon are suggested to be probable replacement of Cu interconnect as they are prone to problems encountered due to technology scaling down. Also they offer superior properties like high thermal conductivity and current carrying capacity compared with copper interconnects.The advanced on-chip interconnects have been analysed at 22nm technology node. It is analysed from the current research work that graphene interconnects possess better performance than copper interconnects. Various performance improvement techniques like conventional CMOS buffer insertion and Schmitt trigger based buffer insertion techniques have been proposed to mitigate the issue of signal integrity for on-chip interconnects. Even optimization techniques like colliding bodies optimization (CBO) technique have been incorporated for the enhancement of tube density of mixed wall carbon nanotube bundle (MWCB) interconnects. Furthermore, modelling technique like finite difference time domain (FDTD) technique has been suggested which gives a close agreement of 2-3 % maximum delay variation with simulated SPICE results. As the technology shrinks, variation due to temperature, fabrication process and environmental fluctuations grows up significantly. This results in variation in output performance. Variability analysis for graphene interconnects has been proposed with various methods like process corner, parametric analysis and Monte Carlo. Timing uncertainty issues like jitter, eye crossing parameter and eye opening factor have been examined for on-chip MLGNR interconnects in the present research work.