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Design of CMOS voltage controlled oscillator for high tuning range
(Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
The main objective of the work is to design a CMOS voltage controlled oscillator for higher tuning range. Today there is a great need for multi-standard wireless receivers in the wireless communications. A receiver is to ...
Analysis of charge injection in a MOS analog switch with impedance on source side
(Dhirubhai Ambani Institute of Information and Communication Technology, 2012)
Turning off of a transistor introduces error voltage at the output of Sample and Hold circuits
which are the key components of Analog to Digital Converters (ADCs) and hence limits their
accuracy of performance in high ...
Built-in self test architecture for mixed signal systems
(Dhirubhai Ambani Institute of Information and Communication Technology, 2009)
Built-in self test architecture or BIST as we call them, are the necessity of time since the shrinking sizes of component on-chip with advance in IC technology are making it BIST artistries are being rapidly developed and ...
Capacitor mismatch in switched capacitor circuits, techniques to minimize mismatch
(Dhirubhai Ambani Institute of Information and Communication Technology, 2011)
This thesis about the designing of capacitive mismatch insensitive switched capacitor amplifier for analog to digital converters (ADC). The accuracy of the conversion is an important factor. The accuracy depends upon the ...
Design and layout of single bit per stage pipelined ADC
(Dhirubhai Ambani Institute of Information and Communication Technology, 2011)
The concept of pipe-lining, often used in digital circuits, can also be applied in the analog domain. It helps to achieve higher speed where several operations must be performed serially. In this work, pipe-lining is ...
High speed, low offset voltage cmos comparator
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
The Analog to digital converters are the key interface blocks between the continuous time domain and the discrete-time digital domain. The performance of high-speed data conversion and digital communication interfaces is ...
Novel 7T SRAM cell design for low power cache applications
(Dhirubhai Ambani Institute of Information and Communication Technology, 2012)
Scaling in integrated circuit technology directly paves way to increased package density,
thereby increasing onchip power. With continuous scaling, low power design techniques
results in efficient use of silicon die. ...
Design of low voltage high performance voltage controlled oscillator
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
In this thesis an ultra low voltage differential capacitive feedback VCO is being proposed .The VCO operates at very low supply voltage of 0.6V.The VCO uses techniques like Forward Body Bias (FBB), and capacitive feedback ...