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Now showing items 11-12 of 12
Designing of an efficient power clock generation circuit for complementary pass-transistor adiabatic logic carry save multiplier
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
This thesis presents a novel four-phase power clock generator for low power adiabatic logic without using inductors. The power clock generator is designed using current mirror arrangement of PMOS and NMOS transistors. ...
Investigating into a light-weight reconfigurable VLSI architecture for biomedical signal processing applications
(Dhirubhai Ambani Institute of Information and Communication Technology, 2019)
The Body Sensor Network systems consist of signal acquisition and processing blocks along with Power Management Unit and radio transmission capabilities. The high power consumption of the radio transmission is often ...