1. DRSR@DA-IICT

Browsing by Subject Random access memory

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Showing results 1 to 6 of 6
PreviewIssue DateTitleAuthor(s)
200811026.pdf.jpg2010Column decoder for memory redundant cell arrayNagchoudhuri, Dipankar; Nahar, Pinky
200611042.pdf.jpg2008Design of a high speed I/O bufferParikh, Chetan D.; Rathore, Akhil
200811025.pdf.jpg2010Design of row decoder for redundant memory cell (SRAM)Nagchoudhuri, Dipankar; Mishra, Ashwini Kumar
200611043.pdf.jpg2008Low power SRAM designDubey, Rahul; Bambhaniya, Prashant
201011008.pdf.jpg2012Novel 7T SRAM cell design for low power cache applicationsNagChoudhuri, Dipankar; Joshi, Srawan Kumar
201111006.pdf.jpg2013Study of power in CR-SRAM in context of precharge reference voltage.Zaveri, Mazad S; Rupapara, Kripal D.
Showing results 1 to 6 of 6