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Browsing by Subject Very large scale integration

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Showing results 1 to 14 of 14

Preview	Issue Date	Title	Author(s)
	2009	Analysis and modeling of power distribution network and decoupling network design strategies for high speed digital and analog VLSI system	Mandal, Sushanta; Nagpal, Raj Kumar; Nagchoudhuri, Dipankar; Pathak, Abhishek
	2009	Built-in self test architecture for mixed signal systems	Mandal, Sushanta; Nagchoudhuri, Dipankar; Jain, Mahavir Rajmal
	2013	CTS and CCOpt metodology's to achieve low skew-low power clock.	Bhatt, Amit; Sreekanth, M.
	2008	Design of a CMOS variable gain amplifier	Parikh, Chetan D.; Verma, Vivek
	2008	Design of low power and high speed decoder for 1MB memory	Nagchoudhuri, Dipankar; Gupta, Punam Sen
	2008	Design of low-voltage, low-power, wide-band CMOS LC VCO using active inductors	Parikh, Chetan D.; Sesha Sai, Aduru Venkata Raghava
	2010	Design of the high speed, high accuracy and low power current comparators	Parikh, Chetan D.; Chasta, Neeraj Kumar
	2008	Designing of an efficient power clock generation circuit for complementary pass-transistor adiabatic logic carry save multiplier	Nagchoudhuri, Dipankar; Mandal, Sushanta Kumar; Ranjith, P
	2006	Efficient scan-based BIST scheme for low heat dissipation and reduced test application time	Nagchoudhuri, Dipankar; Shah, Malav
	2010	High speed sample and hold circuit design	Parikh, Chetan D.; Dwivedi, Varun Kumar
	2019	Investigating into a light-weight reconfigurable VLSI architecture for biomedical signal processing applications	Mishra, Biswajit; Jain, Nupur
	2007	Low power improved full scan BIST	Nagchoudhuri, Dipankar; Parashar, Umesh
	2008	Low power SRAM design	Dubey, Rahul; Bambhaniya, Prashant
	2012	Study of the effectiveness of various low power techniques on sequential and combinational gate dominated designs	Bhatt, Amit; Rana, Kunj

Showing results 1 to 14 of 14