Implementation of ALU using RTL to GDSII flow and on NEXYS 4 DDR FPGA board

Abstract

An ALU is the major part of the CPU which performs various arithmetic and logical operations. It is one of the most frequently used modules in the processor. This paper presents the implementation of 8-bit ALU using RTL to GDSII stream. The tools used for implementation are Cadence tools, Genus and Innovus. The technology node used for implementation is the 45nm technology node and 180nm technology node. The major focus of this thesis is the design optimization in terms of area, delay and power as the industry demands the chips with high speed and low power. Further, the results of both 45nm and 180nm has been compared. The improvement by using 45nm technology in area is 89.59%, in delay is 43.23% and in power is 4.56%. In addition to that, the implementation of 4-bit ALU is done on the FPGA board. The board used is the NEXYS 4 DDR FPGA board.