All Digital ECG Front End ASIC

Abstract

The research presents a continuation work of low power front-end digital electrocardiogram (ECG) acquisition system, designed and simulated (with Wilson Central Terminal ECG Database) using 0.18 mm CMOS technology model files at 0.5 V as the system is operated in sub-threshold region for low power consumption. Furthermore to detect the abnormalities in the heart, a digital code is generated by integrating time to digital converter (TDC) with the designed architecture and retracing of the ECG signal in MATLAB is carried out to check the accuracy of the previously designed architecture and of counter-based TDC which can be observed from the correlation between the retraced signal and the original signal. The correlation factor for the previously designed architecture observed for three patients of theWilson Central Terminal ECG Database is 0.9967, 0.9907, and 0.9881. The correlation factor for the counter-based TDC is 0.9913. In the ASIC design process, the layout of the basic sub-circuits of the architecture is implemented.