FM based pipeline ADC

Abstract

This thesis aims at designing a new architecture for an FM based pipelined Analog to Digital Converter (ADC). It is based on the fact that power is a function of voltage and therefore handling with voltage becomes a difficult task when trying to achieve low power consumption. The idea is to change the very basis on which an ADC works, that is voltage. For frequencies can be generated up to large values without much power consumption. FM based Flash ADCs have been worked upon with power and size reduction for the last decade. An FM based pipelined ADC consists of a mixer and a frequency comparator. The comparator functions by filtering and then converting the signal to a DC value, followed by a digital inverter. The inverter decides the flipping action to zero or one. The mixer is a passive one which generates a subtracted signal with other harmonics as well. As inverter is the only active component and hence this ADC is suitable for low power applications.