Q-Learning Accelerator Chip Design for Robot Path Planning

Abstract

A variety of frameworks and set of tools used for creating complex and difficult behaviours are provided by reinforcement learning in robotics. Q-learning is one of the most popularly used algorithms in reinforcement learning. The implementation of this algorithm is mostly done in MATLAB and Python using various tools and libraries available there. These types of implementations are software based only, which actually requires more time to provide the output. Another way is to implement the algorithm on hardware i.e., to implement it on Field Programmable Gate Arrays (FPGA) or to design a chip based on the applications. This way of implementation reduces the processing time and provides a fastersimulation compared to the one done on software. This thesis aims to reduce the processing time i.e., latency required for the agent to perform an action in any particular state while performing in an episode. We propose an efficient hardware architecture that incorporates the testing of the algorithm and provides a reduction in processing time. We also provided a chip design based on the proposed hardware architecture. This in turn will increase the performance and accuracy of the application. Thus, we majorly focus on the two parameters i.e., latency and accuracy.