Design of a low power high slew rate OPAMP and to study its impact on sigma delta modulator's performance

Abstract

This thesis presents the work done on the design of a low-power, high slew rate opamp and subsequently the design of a fully-differential second order Switched-Capacitor architecture of a Sigma Delta modulator in 1.8 V, 0.18 micron CMOS process.

A nonsaturated differential input stage is used as an adaptive bias circuit in a Super Class AB opamp, implemented in fully-differential configuration using high swing cascade mirrors. Comparator and clock generating circuit are also designed for the modulator.

Various design aspects such as clock feed through, charge injection and KT/C noise have been taken into consideration while designing the modulator. Inaccurate and Incomplete charge transfer in integrator due to bandwidth and slew rate limitations results in gain error and harmonic distortion respectively in the modulator output. Thereby reducing the Signal to Noise and Distortion Ratio of the modulator. Hence Slew rate must be large enough so that the distortion introduced falls below the noise floor of the modulator.

Simulation results show that the amplifier has a very small static power dissipation of 0.54 mW, it can supply a maximum output current of 0.65 mA and static power dissipated by sigma delta modulator is 2.7 mW.