Receiver amplifier design using CMOS current feedback amplifier and current conveyors

Abstract

In the world of high-speed communications, systems involving high-speed data transfer require circuits with innovative features for good performance in terms of speed and power consumption. These data transfer systems constitute of large number of data channels each constituting of driver unit, transmission lines and a receiver unit. The receiver unit has small differential signals as the input. The designed receiver amplifier is required to have wide bandwidth, large slew rate and at the same time, capability to convert the differential input signal to single ended amplified signal without much distortion. For large number of data channels, it is also required that the power consumption of the receiver unit is minimal.

In this work, a model for the receiver amplifier design is implemented using a closed loop amplifier and a differential to single ended converter. Current feedback amplifier is selected for the design of the closed loop amplifier due to their advantages over other topologies in high-speed design. Current feedback amplifiers have current on demand architecture that provides them dynamic current from the supply rails for charging or discharging load for large input signals. The differential to single ended converter is designed using two translinear positive second generation current conveyors. Translinear current conveyors due to their simple circuitry and dynamic current supply during large input signals are able to provide large bandwidth and low loss of signal resulting in very high-speed signal processing. The amplifier model is implemented in MOSIS 0.5 µm single-well technology using BSIM 3.0 model parameters. The obtained results are discussed in the end along with comments on the performance of the current mode circuits involved – current feedback amplifier and current conveyor.