Reconfigurable application specific instruction set processor for kalman filter (R-ASIK)

Abstract

Kalman filter is one of the most important signal processing algorithms used in many tracking applications. The main challenges for hardware implementation of Kalman filter include compute intensiveness O (n3) of the algorithm, numerical sensitivity to rounding errors and huge data I/O requirements. These challenges severely limit its use in high speed, real-time tracking applications that require very small iteration times. This work proposes a novel reconfigurable architecture for the VLSI implementation of Kalman filter, coined as Reconfigurable Application Specific Instruction Set Processor (ASIP) for Kalman Filter (R-ASIK). The R-ASIK architecture is based on the concept of ‘Reconfigurable Systolic Arrays (RSA)’ and provides a real-time implementation by computing a single iteration of the filter in just 15(n + 1) clock cycles using only n(n+1) processing elements, where n is the order of the filter. Other unique features of R-ASIK include increased robustness to rounding errors and resolving the data I/O problem. Reconfigurable feature in R-ASIK architecture provides the flexibility of mapping filters of different sizes ‘n’, on the same architecture. This is a unique feature and does not exist in current literature. A novel architecture to compute transpose of a matrix in only one clock cycle is also presented. The VLSI implementation of R-ASIK was done in three steps namely, modelling the R-ASIK using Verilog HDL, logic synthesis and physical synthesis. The implementation methodology presented for logic and physical synthesis resulted in efficient implementation of R-ASIK in silicon. R-ASIK was mapped to four target technologies (180,130, 90 and 65 nm) and the synthesis results are analyzed. Physical synthesis of R-ASIK was carried out for 180 nm technology. R-ASIK works at 50 MHz clock, which is quite high for a data path intensive algorithm like Kalman filter.