Please use this identifier to cite or link to this item: http://drsr.daiict.ac.in//handle/123456789/149
Title: Investigation of low power design of left-right leap frog array multiplier
Authors: Nagchoudhuri, Dipankar
Sankar, K. Ravi
Keywords: Low voltage integrated circuits
Low voltage integrated circuits - Design and construction
Low voltage systems
Design and construction
Linear integrated circuits
Linear integrated circuits
Electronic circuit design
Issue Date: 2007
Publisher: Dhirubhai Ambani Institute of Information and Communication Technology
Citation: Sankar, K. Ravi (2007). Investigation of low power design of left-right leap frog array multiplier. Dhirubhai Ambani Institute of Information and Communication Technology, ix, 56 p. (Acc.No: T00112)
Abstract: This thesis addresses the Low Power design of 12 bit LRLFAM at the Layout, circuit and logic levels. A new Low power Booth-Recoder (BR), and Multiplexer based partial product generated are designed using pass-Transistor logic. Several 1-Bit full adders are studied: Transmission gate, 10T, 14T, 16T, Multiplexer based and 22T. Experiments show that all these adders produce glitches when used in LRLFAM. A 22T adder is designed that best suits the LRLFA architecture. Floor planning is done with minimum interconnect length has primary aim. LRLFA architecture presented in the literature is modified to reduce the glitches and delay by adding sign extension bits in later stages than in the first row. All the layouts are done using MAGIC 7.1 for TSMC 0.25u technology. Simulations are done using L.T Spice.
URI: http://drsr.daiict.ac.in/handle/123456789/149
Appears in Collections:M Tech Dissertations

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