Design of low power and high speed decoder for 1MB memory

Abstract

Technology scaling is accompanied by rise in leakage power dissipation. This thesis proposes a voltage controllable circuit in the feedback path of the decoder, which drastically reduces the standby leakage current with minimum loss in speed and slightly overheads in terms of chip area. This circuit generates slightly lower supply voltage when the load circuitry is in the standby mode thereby raises the Vt of the CMOS transistors and hence reduces leakage power dissipation The overall power dissipation of a 7x128 decoder is reduced from 0.928mW to 0.584mW for 1Mb Memory with voltage controllable circuit, namely 37% lowering in power dissipation. The operating voltage for the design is 1.2 V. Layout is done in magic 7.1 version in 180nm technology. The simulations are done in LT spice.