High-speed 512-point FFT single-chip processor architecture

Abstract

This thesis present a fully parallel novel fixed point 16-bit word width 512 point FFT processor architecture. The 512 point FFT is realized by decomposing it into three 8 point FFT units. This approach reduces the number of required complex multiplication compared to the conventional radix-2 512 point FFT algorithm. It uses an ROM unit for storing the twiddle factor. The proposed architecture is designed in XILINX 8.2i using Verilog and it is functionally verified with the MATLAB. The floorplanning and timing estimation of each basic module of the proposed architecture is done based on the macro element at 0.25 CMOS technology. The core area of this chip is 99.02 mm2. The processor compute one parallel to parallel (i.e. when all input data are available in parallel and all output data are generated in parallel) 512-point FFT computation in 422 clock pulse in 4.69sec at 90 MHz operation.