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Issue Date
Title
Author(s)
2009
1v rail to tail operational amplifier design for sample and hold circuits
Parikh, Chetan D.
;
Kumar, Mahesh
2008
Designing of an efficient power clock generation circuit for complementary pass-transistor adiabatic logic carry save multiplier
Nagchoudhuri, Dipankar
;
Mandal, Sushanta Kumar
;
Ranjith, P
Discover
Author
1
Kumar, Mahesh
1
Ranjith, P
Subject
1
Bipolar integrated circuits
1
Bipolar transistors
1
Integrated circuits
1
Linear integrated circuits
1
Logic circuits
1
Operational amplifiers
1
Very large scale integration
Date issued
1
2008
1
2009
Has File(s)
2
true