Reduction of power using innovative Clock Gating and Multi Vth techniques in digital design

Abstract

Low power is one of the most important issues in today’s ASIC (Application Specific Integrated Circuit) design. As the transistors scale down, power density becomes high and there is immediate need of reduction in power. There are different techniques available for reduction of power like Operand isolation (OI), Clock Gating (CG) and Multi Vth Library Utilization (MVLU). In this report, we present two approaches for power reduction. The first approach gives two algorithms that show how power and performance matrix is improved compared to conventional MVLU technique. In the second approach, it shows the implementation of constrained fanout clock gating and its benefits over conventional clock gating techniques in ASIC design methodology. This report also presents two analyses. The first analysis shows how the design metrics area, power and performance change due to different techniques of low power (Operand Isolation, Clock Gating and Multi Vth Cell Utilization). The second analysis demonstrates the effect of different CG cells in design and presents how the same design metrics are affected for each CG cell. There are two variations in each CG cell, one is with Reset and the other is without Reset. In this report, we also demonstrate how the design metrics are affected by insertion of Reset signal in each CG cell