Please use this identifier to cite or link to this item: http://drsr.daiict.ac.in//handle/123456789/382
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dc.contributor.advisorZaveri, Mazad S
dc.contributor.authorChhaya, Vaibhav
dc.date.accessioned2017-06-10T14:39:40Z
dc.date.available2017-06-10T14:39:40Z
dc.date.issued2012
dc.identifier.citationChhaya, Vaibhav (2012). CMOS current-based mixed-signal architecture for vector-matrix multiplication. Dhirubhai Ambani Institute of Information and Communication Technology, 40 p. (Acc.No: T00345)
dc.identifier.urihttp://drsr.daiict.ac.in/handle/123456789/382
dc.description.abstractIn present days electronic devices become faster. Computations like vector matrix multiplication become more and more compliant and lengthy. For that CMOS based vectormatrix multiplication architecture, with external digital interface and internal current-based analog operation is presented here. The basic circuits within this architecture are: a binary multiplier that contains a static memory, a current source, a current accumulator and current-to-voltage convertor. The external operand arrives sequentially, so a serial-to-parallel shift-register memory is also implemented. In LTSpice, using 180nm CMOS technology, I have implemented a vector-matrix multiplier circuit that simultaneously performs 64×4 binary multiplications.
dc.publisherDhirubhai Ambani Institute of Information and Communication Technology
dc.subjectCMOS
dc.subjectLTSpice
dc.subjectVectormatrix multiplication architecture
dc.classification.ddc621.39732 CHH
dc.titleCMOS current-based mixed-signal architecture for vector-matrix multiplication
dc.typeDissertation
dc.degreeM. Tech
dc.student.id201011009
dc.accession.numberT00345
Appears in Collections:M Tech Dissertations

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