Low power ASIC design using CPF

Abstract

In recent years, with remarkable growth in personal computing devices, consumer electronics and communication devices, there has been seen urgent requirement for high speed computation and increased functionality. The mobile computing and communication devices are examples of it. But with that power dissipation has immerged as a critical design parameter. In fact in case of portable and battery operated devices, power consumption has become overriding performance constraint than the speed and functionality.

Power consumption is consisting of two parts – Dynamic Power and Leakage Power. In the initial years of development, dynamic power was dominating in total power consumption. But in past few years, greater attention has been given to miniaturization. The technology node is shrinking every year. This has led to increase in leakage power consumption. For technologies below 100nm, leakage power has become dominant part of power consumption.

This thesis is concerned about reduction in leakage power consumption. There are various techniques devised for that. The thesis is concentrated on power shut off (PSO) technique. Power shutoff technique is considered the most effective technique to reduce the leakage power. It includes shutting off modules in design which are going to be idle for some time. With the increase in complexity of design, PSO implementation has become difficult task for designers. Common Power Format (CPF) is a standard format devised by Si2, which helps describe power intent of a design in a standard format. This CPF format has been used to implement PSO technique on three different designs and power reductions have been analyzed for them.