Development of verification environment for multiply-accumulate unit using system verilog

Abstract

Nowadays, Application Specific Integrated Circuit (ASIC) design are becoming complex, even designs based of Field Programmable Gate Array (FPGA) are also complex. So it is very difficult to verify the design through waveform or log files. For that, some self-checking environment is needed to verify the functionality of the design.

In my thesis work, I have worked upon developing the verification environment using System Verilog. In signal processing, most of the transformation uses multiply and addition function frequently. So Multiply-Accumulate (MAC) is the dedicated hardware to improve the speed of Digital Signal Processor (DSP). In this thesis, I have written a Verilog HDL code for MAC unit of DSP in ModelSim SE 6.3f and synthesized in Xilinx ISE 8.1i. System Verilog is used to verify MAC unit. Simulations are done using tool named ModelSim SE 6.3f of Mentor Graphics®. The constrained-randomised inputs and direct inputs are fed to the Design Under Test (DUT) as well as reference model. The output from both systems are compared to check functionality. The functional coverage and code coverage are measured for correctness of the design. The constrained random vectors and direct test cases are used to achieve higher coverage.