Timing aware asic design flow (RC physical)

Abstract

Lack of communication between frontend and backend designers is the most important issue in today�s ASIC (Application Specific Integrated Circuits) design. The frontend designers lack knowledge about the long wires which actually appear when the design is actually placed. So many iterations will occur between frontend and backend in order to achieve timing closure. As the technology is shrinking down rapidly, the communication gap between frontend and backend is increasing further as the contribution to delay by wires is increasing further to a great extent. In order to solve this there should be a communication between frontend and backend about the long wires which are actually placed after placement of the standard cells in the design at the physical synthesis level. Also designers should have thorough understanding of libraries and best optimum techniques while placing the design in the backend. In this report the structure of the libraries and various parameters in libraries have been discussed. The best floorplan, Placement and clocking strategies have been discussed and also been implemented on DTMF (Dual Tone Multi Frequency) chip. The best synthesis methodology RC Physical, in which the backend information will be available at the synthesis stage itself, has been implemented on the Open MSP processor and also the correlation gap between frontend and backend with respect to other synthesis methodologies have been discussed.