Please use this identifier to cite or link to this item: http://drsr.daiict.ac.in//handle/123456789/46
Title: Design of CMOS front end for 900MHz RF receiver
Authors: Bhatt, Amit
Harshey, Jitendra Prabhakar
Keywords: Circuit design
Complementary metal oxid semiconductor (CMOS)
CMOS
Radio frequency
RF receiver
Simulation
Issue Date: 2004
Publisher: Dhirubhai Ambani Institute of Information and Communication Technology
Citation: Harshey, Jitendra Prabhakar (2004). Design of CMOS front end for 900MHz RF receiver. Dhirubhai Ambani Institute of Information and Communication Technology, vii, 98 p. (Acc.No: T00009)
Abstract: Portable wireless personal communication systems such as cellular phones, message pagers, and wireless modems traditionally have been built from a mixture of IC technologies. In fact if we section a commercial cellular phone, we could find many separate ICs together linked in the analog section. Moreover some of these ICs are realized on GaAs substrate, others on bipolar Silicon and only the digital section is integrated on CMOS substrate. One of the main challenges facing complete integration of receiver (transmitter) hardware has been a lack of suitable on-chip RF and IF filtering. This approach increases system complexity, cost, and power consumption. The aim of this thesis consists in the investigating the characteristic of RF building blocks that constitute an integrated RF receiver. This thesis, is the balance between microelectronic and microwave, and investigates the bottlenecks in the fully integration of an RF receiver, and is particularly focused on the design of high quality passive devices and high performance low noise amplifiers. This receiver is part of a single chip transceiver, which operates in the 902-928 MHz ISM band. The receiver combines a balanced low-noise amplifier; down conversion mixers, low pass channel-select filters, and IF amplifiers all in one single CMOS IC. Noise components of MOS at high frequencies were studied in detail. Device properties unique to CMOS are exploited to obtain highly linear RF circuits. In design of low noise amplifier, I concentrated my efforts on minimizing the value of passive devices so that all of them can be fabricated on single chip. For this I undertook several optimizations and tradeoffs. Particularly the noise power trade-off with inductors value was stressed on. LNA had three primary design specifications of input impedance matching, gain and noise. I also experimented on several techniques of input match. The results obtained are suited to the needs fairly well. In the mixer design, my primary goal was to design a doubly balanced mixer for single ended inputs. This was necessitated because the antenna signal received was single ended before the LNA and even in LNA, due to several considerations; I obtained a single ended output. Finally this report contains all my designs and simulation results.
URI: http://drsr.daiict.ac.in/handle/123456789/46
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