Design of AHB-Wishbone bridge

Abstract

System-on-Chip (SoC) design is performed through integration of pre-designed components, called intellectual Property (IP). Design reuse is a critical feature in SoC design. Design reuse is the simple concept of using IP Cores of proven designs over again and again.

IP Cores may adhere to different interface standards. This leads to incompatibility between IP Cores. This requires the creation of custom glue logic to connect each of the cores together. A Bridge ensures that IP Cores can be reused with confidence in a multitude of systems supporting different bus protocols. Its purpose is to foster design reuse by alleviating System-on-Chip integration problems. This improves the portability and reliability of the IP Cores and system, and results in faster time-to¬-market for the end user.

The function of ARB-Wishbone Bridge is to map the control and address signals from one bus to another. The AMBA ARB is for high-performance, high clock frequency system modules. The ARB acts as the high-performance system backbone bus. ARB supports the efficient connection of processors, on-chip memories and off¬ Chip external memory interfaces. The Wishbone System-on-Chip (SoC) Interconnection Architecture for IP Cores is a flexible design methodology for use with semiconductor IP cores.