Please use this identifier to cite or link to this item: http://drsr.daiict.ac.in//handle/123456789/504
Full metadata record
DC FieldValueLanguage
dc.contributor.advisorZaveri, Mazad S
dc.contributor.authorRangani, Jaydeep
dc.date.accessioned2017-06-10T14:41:56Z-
dc.date.available2017-06-10T14:41:56Z-
dc.date.issued2014
dc.identifier.citationRangani, Jaydeep (2014). HDL implementation of associative memory based instruction predictor for power reduction. Dhirubhai Ambani Institute of Information and Communication Technology, viii, 41 p. (Acc.No: T00467)
dc.identifier.urihttp://drsr.daiict.ac.in/handle/123456789/504-
dc.description.abstractNow a days, power consumption in digital integrated circuits/systems is a major issue. The goal here is to reduce power consumption, by assuming the circuit is divided in different power consuming modules, observing their operations and selectively turning ON/OFF these modules. We propose to use Associative Memory (AM) for selectively turning ON/OFF these modules. Based on the statistics of operations of these modules, we have used Associative Memory to develop and implement a power reduction module. The thesis is concerned with reduction in power consumption by using AM. There are various applications for which AM is currently used. Here, the effort is concentrated on reducing power consumption by utilizing AM for data prediction. This technique has been found to be the most effective to reduce power consumption. The design provides the ability to turn OFF modules which are going to be idle for some time. There are many power consuming systems in which power consumption can be reduced by using the proposed Associative Memory Based Power Saver (AMBPS). This device can monitor power consumption in different equipment to save power. The power consumption of this device is 10.499mW and operate this device at max frequency 222.22MHz.
dc.publisherDhirubhai Ambani Institute of Information and Communication Technology
dc.subjectHDL Implementation
dc.classification.ddc621.392 RAN
dc.titleHDL implementation of associative memory based instruction predictor for power reduction
dc.typeDissertation
dc.degreeM. Tech
dc.student.id201211035
dc.accession.numberT00467
Appears in Collections:M Tech Dissertations

Files in This Item:
File Description SizeFormat 
201211035.pdf
  Restricted Access
1.43 MBAdobe PDFThumbnail
View/Open Request a copy


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.