All-digital time based analog-to-digital converter and time-to-digital converter

Abstract

The goal of this thesis is to design a fully digital sensor interface. For this, a time-based analog to digital converter and time to digital converter has been investigated. It is concluded that fully digital time-based ADC architecture also yields itself as an TDC with architectural analysis alone. The advantage of the proposed architecture is that it configures the core to function as both ADC and TDC. The resolution of both as TDC as well as ADC and the resolution to be settable. The fully digital circuit has a ring delay line (RDL), latch, encoder and a synchronous counter. The circuit is implemented in 0.18mmdigital CMOS, achieving 139mV/LSB (14-bit, 1-MS/s, 1.6 mW) in ADC mode and 227 ps/LSB (Vin = 1.0 V, 14-bit), 94 ps/LSB (Vin = 1.8 V, 14-bit) in TDC mode respectively.