D-latch based low power memory design

Abstract

Low power consumption is the main attraction of the digital circuit design in the Sub threshold region of operation. In this region of operation less energy is consumed for active operation and less leakage power is dissipated than higher voltage alternatives. As a trade-off circuits operate slowly because the supply voltage is less than the threshold voltage of the transistors. Sub-threshold operation is considered as an effective solution in designs where low power consumption is the prime concern and operating speed can be sacrificed. The sub-threshold systems need the same voltage level operated memory design. Also, the sub-threshold memory design must be robust in terms of SNM (signal to noise margin) as the operating supply voltage is few hundreds of millivolts depending on technology node. This demands the architecture that ensures the effective data read/write operation under all critical conditions. This research work mainly focuses on D-Latch based 128 Byte full custom memory array and memory controller design. Starting with different latch architectures’ minimum operating supply voltage comparison, the complete Byte addressable memory design flow including row/column decoder design, memory controller design has been discussed. The complete layout of the memory, performance results under an application and its different parameters have also been included in the report. All the design parameters and the simulation results are produced for 0.18μm process.