Study of communication schemes for multiple neural processing nodes

Abstract

Over the past few years variety of hardware for implementing Artificial Neural Networks (ANN) has been designed. The most basic approach to speed up any ANN algorithm, is to parallelize processing. However, the existing wired strategies are not easily scalable and are also expensive. This thesis aims to provide low cost, easily scalable architecture for implementation of ANN, targeted for microcontrollers and FPGA architectures. With wired strategies, it is difficult to have scalable architecture with multiple Processing Nodes (PNs). Scalability of the same architecture can be improved by enabling wireless communication between the PNs. In this thesis, different strategies for implementation ofANNhave been analyzed, which considers two different types of PNs (Arduino R and Spartan3E R ) and various communication strategies (I2C with different speeds, Zigbee beacon enabled, Zigbee Non-beacon enabled, Zigbee GTS mode and TDMA scheme). Comparison of all these communication protocols have been carried out in terms of performance (speed) and energy. In this thesis, Nearest-Neighbour-Mesh (NNM) structure for the implementation is considered, where an application consists of 1024 neurons and 1024 synapses per neuron. The analysis has been carried out by varying number of PNs available for implementing this application. For simulation of all the wireless strategies, NS2 (Network Simulator) is used. For estimating computation time for Arduino and Spartan3E, Arduino software (Arduino 1.6.2) and Xilinx ISE Design Suite 14.7 R is used, respectively.