Design of frequency synthesizable delay locked loop

Abstract

As the speed performance of VLSI systems increases rapidly, more emphasis is placed on suppressing skew and jitter in the clocks. Phase-locked loops (PLLs) and delay-locked loops (DLLs) have been typically employed in microprocessors, memory interfaces, and communication IC's for the generation of on-chip clocks. But phase error of PLLs is accumulated and persists for a long time in a noisy environment, that of DLL's is not accumulated, and thus, the Clock generated from DLLs has lower jitter. Therefore, DLLs offer a good alternative to PLL's in cases where the reference clock comes from a low¬ jitter source, although their usage is excluded in applications where frequency tracking is required, such as frequency synthesis and clock recovery from an input signal. Also, the DLLs adjust only phase, not frequency, so the operating frequency range is severely limited. Much work is done to improve the operating range of DLLs, but very less work is done to make DLLs frequency synthesizable. Here, frequency synthesizable DLL is implemented in simplest manner so that it can be useful with least complexity.