Please use this identifier to cite or link to this item: http://drsr.daiict.ac.in//handle/123456789/605
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dc.contributor.advisorParekh, Rutu
dc.contributor.authorKale, Vishwamber N.
dc.date.accessioned2017-06-10T14:44:20Z
dc.date.available2017-06-10T14:44:20Z
dc.date.issued2016
dc.identifier.citationKale, Vishwamber N. (2016). Design of 64-bit SRAM using single electron transistor. Dhirubhai Ambani Institute of Information and Communication Technology, viii, 39p. (Acc.No: T00568)
dc.identifier.urihttp://drsr.daiict.ac.in/handle/123456789/605
dc.description.abstractThe present day devices demand memory chips with larger size and smallphysical dimensions. This drives the designer to design high density memorydevices. The memory designed using CMOS technology do not have comparablespeed to match with the speed at which processor operate. Hence, we aretargeting to design high speed SRAM using Single Electron Transistor (SET). SETconsumes ultra low power. SET circuits can be stacked above the CMOS platform.The basic components of SRAM are decoder, sense amplifier, control block,write circuit driver and 6-T SRAM cell. To design stable SRAM, proper sizingof each transistor is reqiured. Decoder selects memory address for reading andwriting data. So proper designing of decoder is required. Due to high capcitanceof word line, Bitline doesnt get full voltage swing. Therefore, SRAM needs to bedesigned with higher stability. Selection of sense amplifier depends on the rateof bit-line discharging. To generate internal signals within SRAM for performingread and write operations designing a controller circuit is required.To achieve above mentioned specifications, stability of SRAM is verified usingN-Curve. Stability comparison is performed for both CMOS and SET basedSRAM. Dynamic decoders are used in SRAM, as they outperform conventionaldecoder in terms of power and delay. Comparison between SET and CMOS baseddecoder and sense amplifier is performed in terms of power and delay. Controllerdesign for generating internal signal for read and write operation is implementedfor both CMOS and SET based SRAM.We have verified the functionality of 64-bitSRAM by simulating read and write operations for SET and 45nm CMOS technology.Access time for SET based SRAM is 121 ps and for CMOS based SRAMis 872 ps. SET based SRAM takes total power as 723 nW and CMOS based takestotal power as 956 mW. In this work, we present SET based SRAM which is fasterand ultralow-power as compared to the 45nm CMOS based SRAM.
dc.publisherDhirubhai Ambani Institute of Information and Communication Technology
dc.subjectSingle Electron Transistor
dc.subjectDynamic Decoders
dc.subjectCircuit
dc.subjectStatic Random Access Memory
dc.subjectSense Amplifier
dc.subjectCMOS
dc.classification.ddc621.39732 KAL
dc.titleDesign of 64-bit SRAM using single electron transistor
dc.typeDissertation
dc.degreeM. Tech
dc.student.id201411018
dc.accession.numberT00568
Appears in Collections:M Tech Dissertations

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