Design of a Real Time Low Power Interrupt Driven Processor With Fair Scheduling

Abstract

"Recent times have seen a considerable amount of growth in the processor industry. The design of a processor is mainly focussed on two aspects namely, high performance or low power. While some high-end applications require greater performance, there are areas such as home automation where the focus is put on making a low cost, low power processor so that it can be used as an aid in our day-to-day activities such as home security, lighting or temperature control etc. In such applications, some tasks take precedence over the other tasks and must be completed within a specified amount of time. This leads to the requirement for a real time processor. Also, as different tasks have their respective priorities, the lower priority tasks might not get a chance to finish if we use the conventional priority based scheduling algorithms. Thus, we have devised a fair algorithm which increases the chance of lower priority tasks to finish. This is implemented by the interrupt controller unit designed along with the processor (core). As a complete system is to be made, there needs to be a medium which facilitates the communication between the sensors and the processor. This is accomplished by the implementation ofWishbone bus. To make our processor low power, we have made a wake-up interrupt controller (WIC) unit that switches all the other units off whenever there are no interrupts to be served. Thus, a complete System-on- Chip (SoC) was designed with these modules to implement a real time and low power interrupt driven processor which provides a fair chance to the lower priority interrupts while providing deterministic response to the time critical high priority interrupts. The SoC was designed using Verilog language. The front-end synthesis is performed using Cadence RTL compiler. The technology library used for the front-end analysis is Nangate (45nm)."