Design of Low Power Time-to-Digital Converter in 0.18?m CMOS

Please use this identifier to cite or link to this item: http://drsr.daiict.ac.in//handle/123456789/699

Title:	Design of Low Power Time-to-Digital Converter in 0.18?m CMOS
Authors:	Mishra, Biswajit Agrawal, Jatin
Keywords:	FPGA Implementation Resolution Improvement Technique Ring Delay Line
Issue Date:	2017
Publisher:	Dhirubhai Ambani Institute of Information and Communication Technology
Citation:	Jatin Agrawal(2017).Design of Low Power Time-to-Digital Converter in 0.18?m CMOS.Dhirubhai Ambani Institute of Information and Communication Technology.ix, 45 p.(Acc.No: T00665)
Abstract:	A full custom, all-digital, low power Time-to-Digital Converter (TDC) based on a Time-based Analog to Digital Converter (TAD) is presented. The proposed architecture contains a 20-bit ripple counter, 16-bit latch, an encoder, an edge detector and a Ring Delay Line (RDL) with appropriate control logic circuit. The TDC-IC core has an area of 0.026mm2 in 0.18?m CMOS that achieves resolution of 586.4ps/LSB and 201.8ps/LSB, power consumption of 32.5?W and 315.5?W, with the distance calculation up to 2949.4km and 1015.7km at 1V and 1.8V respectively,making it feasible for distance measurement in space applications.
URI:	http://drsr.daiict.ac.in//handle/123456789/699
Appears in Collections:	M Tech Dissertations

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