Please use this identifier to cite or link to this item: http://drsr.daiict.ac.in//handle/123456789/889
Title: Investigation into radiation hardening techniques on differential receiver and power management unit in 0.8um CMOS for space applications
Authors: Mishra, Biswajit
Kasodniya, Sanjay Kumar
Keywords: CMOS
Radiation hardening techniques
Issue Date: 2019
Publisher: Dhirubhai Ambani Institute of Information and Communication Technology
Citation: Kasodniya, Sanjay Kumar (2019). Investigation into radiation hardening techniques on differential receiver and power management unit in 0.8um CMOS for space applications. Dhirubhai Ambani Institute of Information and Communication Technology, ix, 123 p. (Acc.No: T00828)
Abstract: This report details out radiation hardening techniques, their implementation on Di erential Receiver and Power Management Unit. Dierential Receiver ASIC is designed with addressable, synchronous and asynchronous features called dressableSynchronous/asynchronous Di erential Receiver (ASDR) ASIC. Onboard Payload data handling subsystems use standard bus interfaces (RS422) and protocols (eg. UART) and are available in separate devices. The proposed ASDR implements the RS422 electrical interface for di erential-serial-data reception and has multi-mode synchronous asynchronous serial data handling protocol, as a single chip solution. The design has 5 bit self-address feature, which is useful if these devices are used in multi-drop con guration. Such a single chip solution is of importance for ground based application, in space and related applications. This design is fabricated with 0.18 m CMOS process. Radiation hardening techniques, guard-ring, node-splitting and di erential-charge-cancellation have been implemented in the ASIC. After fabrication, the di erential receiver ASIC has been tested for radiation environment speci c to Single Event E ects and Total Ionizing Dose, with an aim to make it suitable for space applications. To the best of our knowledge this is the rst ever integrated chip that provide interface (both Tx and Rx con guration) with protocol (UART and synchronous serial to parallel) for low speed di erential data communication. A capacitive power management unit (PMU) for a DC energy harvester such as a photovoltaic (PV) is proposed. It is assumed that the input will have a minimal voltage requirement of approximately 460mV and can go up to 800mV , typical output from a PV cell. This is our initial attempt to design a novel PMU based on standard 0:18 m CMOS models to be used for applications (WSN, payload sensors) that require energy autonomy. Power management unit is designed to interface logic circuit with energy harvesters. Radiation hardening technique is used to make this design suitable for space applications. The temperature sensing system on a satellite can use ASDR and PMU for wired and wireless approach respectively.
URI: http://drsr.daiict.ac.in//handle/123456789/889
Appears in Collections:PhD Theses

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