Design and Simulation of Single Electron Transistor Based High-Performance Computing System at Room Temperature

Abstract

"The VLSI technology has seamlessly grown over the years, that yields high-performance, low-power and high-density devices. Over the several decades, the performance of existing complementary metal-oxide semiconductor (CMOS) technology has been constantly improved by scaling of the transistors size. The scaling and heterogeneous 3D integration aids in achieving high density logic. However, the performance of nanometer scale CMOS based designs is limited due to the short-channel effect, leakage current and process variations. There is a trade-off between speed and power consumption that significantly affects the performance of complex designs like computing devices. The nanoelectronics devices having the capabilities of heterogeneous 3D integration and functional integration with existing technologies serves potential solutions to future silicon technology challenges. These devices can overcome the aforesaid problems and escalates the capabilities of electronics devices in terms of speed, power, density, size and volume. The single electron transistor (SET) is a promising and elegant nano-device which possesses several convincing features such as low energy consumption, efficient operational at room temperature, high switching speed, sustainable with scaling and reduced operating potentials to compete or outperform conventional CMOS technology. The SET can be used as basic element in either individual circuit or hybrid circuit with existing CMOS technology. The survey of individual SET based designs shows that these are at smaller block level with improper SET parameters, operating temperature, interconnect parasitics, etc. The bottleneck with SET based designs having thousands of gates, is unavailability of either dedicated electronic design automation (EDA) tool or standard component library or synthesizer. This research gap is accomplished by proposed SET based computing system with consideration of realistic SET parameters and interconnects parasitics at room temperature operation.The SET based computing system design is accomplished by utilizing industry standard Cadence Virtuoso analog design environment (ADE). It is carried out with gate level abstraction of SET Verilog-A behaviour model. The generated SET symbol is used to design basic combinational and sequential elements. The higher order circuit blocks of computing system are realized with these elements. Finally, a computing system is realized with integration of these foundation circuit blocks. The computing system is analyzed for a set of multiple instructions i.e. program level with the help of a developed tool. The proposed design is carried out at transistor level abstraction. The formulated analytical model is performed for SET and it matches very closely with simulation model results. The each of the design block is verified for timing analysis. Also, the parametric analysis is compared with other research works. The proposed SET based computing system is considerably better with higher operating frequency (around 5 times), lower power dissipation (around 1.6 times) and higher execution of instruction per second (around 5 times) than its counterpart 16 nm CMOS technology. To check the robustness of the SET based computing system, variability analysis has been performed. It is observed that SET based computing system is less immune to supply voltage variations. This can be compensated by applying suitable voltage regulation techniques. On the other hand for temperature and process variations, it is envisaged that the SET based computing system is very robust. Hence, it is inferred that variability issues are very lesser in SET based systems and can be good alternative to replace conventional systems. Through the SET based design approach, integrated circuit can pack greater functionality with higher operating speed, smaller footprint, lower power consumption and lesser thermal budget."