Front-end design for two lead ECG acquisition system

Abstract

The research presents a low power front-end design for electrocardiogram (ECG) acquisition system which is designed using 0.18mmCMOS technology with a supply voltage of 0.5V. The proposed architecture provides a fully digital solution to the traditional analog acquisition system. The design removes various analog block such as differential amplifiers, filters and passive elements such as switched capacitors. The design incorporates techniques such as time-domain amplification, moving average filtering and offset cancellation. The MA-VTC block performs the time-domain amplification and moving average filtering. The offset cancellation is provided by a negative feedback network. The system is designed to operate in sub-threshold region for low power consumption. The system provides output TDC signals corresponding to LEAD I and LEAD II signals of an ECG system.