Please use this identifier to cite or link to this item: http://drsr.daiict.ac.in//handle/123456789/989
Title: Device modelling and circuit designing using prominent neural network
Authors: Agrawal, Yash
Diksha
Keywords: Bipolar junction transistor (BJT)
Feed forward neural network
Levenberg marquardt (LM)
Mean square error
Graphene nano ribbon (GNR)
Issue Date: 2020
Citation: Diksha (2020). Device modelling and circuit designing using prominent neural network. Dhirubhai Ambani Institute of Information and Communication Technology. ix, 75 p. (Acc.No: T00904)
Abstract: VLSI system is aggregation of millions of active and passive elements. Determination of different parameters of active elements and accurate value of passive elements for desired output characteristic is undoubtedly a difficult task. Therefore automation in the field of designing and characterization of devices and circuits is one of the key requirements in today’s era. Artificial Neural Network (ANN) plays a crucial role because of its intense power of prediction and capability of solving complex problems. Innovatively tapping the advantages of splendid NN, this has been adopted in the present work for automated designing and optimization of VLSI e-circuits and systems for the required set of output performance parameters. To explore the advantage of NN in the field of VLSI e-circuit, amplifier is designed usingNNapproach for two prominent semiconductor devices viz. bipolar junction transistor (BJT) and metal-oxide-semiconductor field-effect transistor (MOSFET). Due to capability of working of MOSFETs at scaled technology, MOSFET has emerged as strong contender than that of BJT. An ideal Common Source configuration of MOSFET is considered in present work which is designed at 180nm technology node without considering various non-linearity and short channel effect. However, in the advanced nano-era, technology nodes of the order in tens of nanometer are often used. Below 100nm technology leakage current becomes significant and as dielectric gets thinner gate leakage current becomes one of the dominant components of leakage current.To mitigate this issue, prospective GNRFET device is also investigated in the present work. Based on the HSPICE simulations it is observed that OFF leakage current due to scaling of oxide thickness in GNR FETs decreases as we lowers the thickness of oxide. High ratio of ON to OFF current in GNR-FET suggests its extensive utilization for the futuristic circuits.
URI: http://drsr.daiict.ac.in//handle/123456789/989
Appears in Collections:M Tech Dissertations

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