(Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Chhaya, Vaibhav; Zaveri, Mazad S
In present days electronic devices become faster. Computations like vector matrix
multiplication become more and more compliant and lengthy. For that CMOS based vectormatrix
multiplication architecture, with external digital interface and internal current-based
analog operation is presented here. The basic circuits within this architecture are: a binary
multiplier that contains a static memory, a current source, a current accumulator and
current-to-voltage convertor. The external operand arrives sequentially, so a serial-to-parallel
shift-register memory is also implemented. In LTSpice, using 180nm CMOS technology, I
have implemented a vector-matrix multiplier circuit that simultaneously performs 64×4
binary multiplications.
