(Dhirubhai Ambani Institute of Information and Communication Technology, 2011) Patel, Vidyut A.; Parikh, Chetan D.
Nowadays, asynchronous systems are becoming more popular for low power applications. Asynchronous Systems help to reduce metastability errors and clock skew errors. This thesis is about an asynchronous analog to digital converter (ADC) designed for low power. Here, a design is proposed based on successive approximation algorithm with folding circuit. The folding circuit works as a voltage mapping circuit. The proposed ADC can be used with asynchronous systems as well as conventional synchronous systems. The ADC has been implemented for 5 bit resolution for input voltage range of 0.7V to 2V in 180nm technology. It achieves maximum speed of 8MSPS and DNL of 0.5LSB. The power consumption of the ADC is 2.6mW.
