M Tech Dissertations

Permanent URI for this collectionhttp://drsr.daiict.ac.in/handle/123456789/3

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End date: 2009Subject: search.filters.subject.Design and construction

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    Particle swarm optimization based synthesis of analog circuits using neural network performance macromodels
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Saxena, Neha; Mandal, Sushanta Kumar
    This thesis presents an efficient an fast synthesis procedure for an analog circuit. The proposed synthesis procedure used artificial neural network (ANN) models in combination with particle swarm optimizer. ANN has been used to develop macro-models for SPICE simulated data of analog circuit which takes transistor sizes as input and produced circuit specification as output in negligible time. The particle swarm optimizer explore the specfied design space and generates transistor sizes as potential solutions. Several synthesis results are presented which show good accuracy with respect to SPICE simulations. Since the proposed procedure does not require an SPICE simulation in the synthesis loop, it substantially reduces the design time in circuit design optimization.
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    Low drop-out (LDO) voltage regulator without off-chip capacitor
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Agarwal, Gopal; Parikh, Chetan D.
    Designing of Low Drop-Out Voltage Regulators (LDOs) operating without a large off-chip capacitor, having a very good transient response and maintaining the loop stability for full load current range in low supply voltage and low quiescent current environment is a challenging task. The present thesis work proposes a technique to achieve faster loop response during load transients while consuming very less quiescent current. The idea revolves around fast charging and discharging of the large equivalent capacitor at the gate of the pass transistor in response to fast load current transients. The extra circuitry added does not affect the working of main feedback loop in steady state conditions. The idea is inspired from the Nagraj’s idea of achieving high slew rate in operational amplifier which uses an auxiliary circuit to produce large currents in one of the two switching transistors, one for charging and other for discharging the slew rate limiting capacitor in the circuit. A common source amplifier (having i/p v/s o/p characteristic which closely resembles a digital inverter) followed by the large, normally off switching transistor is used here to overcome the slew rate limitation at the gate of pass transistor.
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    Built-in self test architecture for mixed signal systems
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Jain, Mahavir Rajmal; Mandal, Sushanta; Nagchoudhuri, Dipankar
    Built-in self test architecture or BIST as we call them, are the necessity of time since the shrinking sizes of component on-chip with advance in IC technology are making it BIST artistries are being rapidly developed and used for digital circuitry due to well defied fault models and advanced designs tools and techniques available. But with more analog circuitry being built on same platform with digital circuitry, the necessity for BIST architecture of mixed signal system on chip is increasing. The proposed BIST scheme is developed to test the data converters, both DAC and ADC on chip as well as other analog IP modules depending on specification of design without/least affecting the architecture of actual design and without making use of any complex DSP circuitry. The concept of internet node access based testing of digital blocks is also used for dynamic parameter of DAC like offset voltage and gain error, monotonicity and linearity non-specific BIST scheme. Letter the digital control logic protion of SAR ADC is tested with scan-chain insertion and thus overall functionality of SRA ADC is verified. A simple comparison based method is also proposed for other type ADCs. For other anlog IPs, we propose IP-based testing where digital to analog converted test signals can be applied depending on specifications of IP design from vendor without affecting architecture of the design. The output from IPs are taken at different nodes and applied directly to ADC on chip. The digitized output response is then compared with expected response to test the functionality of the DUT and find out its deviation from desired value to achieve pre-defined level of accuracy. The design failing any of the sequence of afore-mentioned test is discarded faulty. The circuitry is designed and evaluated at schematic level using TSMC complementary metal oxide-semiconductor (CMOS) 0.5um technology.
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    Transaction based verification of DA-FIR filter using AMBA AHBTm transactor
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Lad, Umeshkumar Mangubhai; Dubey, Rahul
    Transaction based verification is used for faster verification purpose. Reusable transactors are designed and designs are verified at transaction level using these transactors. The test bench are written in higher level language and applied to design via Transactor. Hardware emulators accelerate the use of transaction advantages for the verification people. A number of SoCs and components can be verified with this methodology. The Device under test (DUT) used here is 5th order signed DA-FIR filter and the Transactor designed is AMBA® AHB™ from ARM. The Transactor is designed as Bus functional model in Verilog and state machine model in C++. The C++ based test bench gives the command (input) for verifying design. The Transactor takes care of the signal needed for applying to DUT. The tool used for the verification is Eve’s ZeBu. The verification environment and methodology has been described and compared with the present scenario. Complexity and speed performance are the main constraints for the comparison.
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    Self-calibrating technique for digital-to-analog converter in successive approximation register analog-to-digital converter
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Patel, Sujit Kumar; Parikh, Chetan D.
    Successive Approximation Register (SAR) analog to digital converter resolution is limited mainly by the capacitor ratio error; comparator offset voltage and capacitor voltage dependence error. A SAR ADC resolution is limited to 10-bit due above errors. Resolution can be increased by using calibration techniques for these errors. From the calibration of capacitor ratio error and comparator offset voltage 16-bit resolution can be achieved. Calibration of capacitor voltage dependence error is necessary for resolution more than 16-bit. This thesis proposes the self calibration technique for capacitor ratio error in differential SAR analog to digital converter. Using this calibration technique capacitor ratio error is minimized. Linear voltage coefficient of capacitor is canceled by the differential SAR ADC but, comparator has limitation of finite common mode rejection ratio (CMRR). In this work self calibration of capacitor voltage dependence error is also discussed in detail.
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    Design of the analog front end circuit for X-ray detectors
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Roy, Subhash Chandra; Parikh, Chetan D.
    The Thesis presents a novel idea to efficiently read out the value corresponding to incident X-Ray, from X-Ray sensor. A system level solution has been proposed which is unique in itself in terms of approach. A simple design of analog front end circuit for 64 channels, consisting of Charge Sensitive Preamplifier (CSP), Pulse Shaping Amplifier (PSA), Peak Detector, subtractor, Mux and ADC has been proposed. In CSP, Transmission Gate (TG) has been used, in parallel with integrating capacitor, where the NMOS is operating in weak inversion, when TG is supposed to be off. It fulfils the requirements like posing very high ac resistance, providing alternative path for DC leakage current signal, discharging integrating capacitor quickly etc. An amplifier cum level shifter has been used to match the output DC level of CSP with input DC level of PSA. PSA has been implemented as a 4th order Bessel-Butterworth low pass filter, which provides good step response, and hence output is obtained with negligible peaking. High pass filter hasn’t been used to avoid low frequency signal loss. A subtractor has been proposed after the peak detector, which is taking care of offset voltages and low frequency noise. This system till the output of shaper is providing a resolution of 1.7% against the specification of 3%.
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    10-bit high speed high SFDR current steering DAC
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Bapodra, Dhairya B.; Parikh, Chetan D.
    The Thesis presents an attempt to design a 10-bit High Speed High SFDR Current Steering DAC with a simple and different approach. Most of earlier approaches contain complex design and bulky unary portion. Here an approach tried that uses sub-segmentation of unary part. By using sub-segmentation of unary part, reduction in complex decoder block can be introduced. The issue of synchronization is tackle by a latch that is previously proposed for tackling very high frequency. Here by segmentation of unary part area as well as complexity is reduced for decoder. And the sentence that is always true “Simpler Designs are faster”. And reduction in complexity leads to reduction in error sources.
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    Design of multi-band fractal antenna for satellite navigation application
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Pathak, Swapna; Gupta, Sanjeev
    Recent efforts by several researchers around the world to combine fractal geometry with electromagnetic theory have led to a plethora of new and innovative antenna designs. This research proposal has been primarily focused in the analysis and design of fractal antenna elements. Fractals have no characteristic size, and are generally composed of many copies of themselves at different scales. These unique properties of fractals will be exploited in order to develop a new class of antenna-element designs that are multi-band and/or compact in size. These key issues are the major motivations for the research project which involves the analysis and design fractal antennas in L, S and C-bands.
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    1v rail to tail operational amplifier design for sample and hold circuits
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Kumar, Mahesh; Parikh, Chetan D.
    At low voltage, the input common mode voltage of Operational amplifier is limited which restricts its use as a buffer. This works deals with designing a rail to rail amplifier. The Thesis presents a 1V rail to rail operational amplifier that has been used as a unity gain buffer in the sample and hold circuit for 1V 10 bit 1MSPS pipeline ADC in 0.18?m technology. The Operational amplifier is designed using dynamic level shifting technique which uses an additional input CM adapter circuit for fixing the input common mode voltage. Novelty in the input CM adapter circuit and a low value of gm fluctuation (�0.245%) has been achieved. The Operational amplifier is implemented in standard CMOS technology. An open loop architecture is chosen for the implementation of sample and hold circuit. The transmission gate switch is used in the sample and hold circuit for reducing the effect of channel charge injection and clock feedthrough. Also, the transmission gate switch offers a low resistance as compared to pMOS or nMOS switches. The sample and hold circuit speed up to 1MSPS has been achieved.
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    Design issues in direct conversion receiver
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Gupta, Amit Kumar; Gupta, Sanjeev
    The wireless system is being rapidly proliferated in our life. The growing of capacity in wireless communication requires a new type of wireless communication method which does not affect current work on circuits and systems that can operate on gigahertz wide signals will undoubtedly be the wave of the future as pressures to supply multimedia services over wireless continue to build. To achieve the goal of single receiver which can act on various different standards the Direct Conversion Receiver (DCR) is the most suitable architecture. The DCR has been known for quite long years. There are number of design issues related to the implementation of DCR. This thesis presents the issues which are related to design of Direct Conversion along with the design issues related to LNA design.