M Tech Dissertations

Permanent URI for this collectionhttp://drsr.daiict.ac.in/handle/123456789/3

Browse

End date: 2009Subject: search.filters.subject.Electronic circuit design

Search Results

Now showing 1 - 10 of 16
  • Thumbnail Image
    ItemOpen Access
    Particle swarm optimization based synthesis of analog circuits using neural network performance macromodels
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Saxena, Neha; Mandal, Sushanta Kumar
    This thesis presents an efficient an fast synthesis procedure for an analog circuit. The proposed synthesis procedure used artificial neural network (ANN) models in combination with particle swarm optimizer. ANN has been used to develop macro-models for SPICE simulated data of analog circuit which takes transistor sizes as input and produced circuit specification as output in negligible time. The particle swarm optimizer explore the specfied design space and generates transistor sizes as potential solutions. Several synthesis results are presented which show good accuracy with respect to SPICE simulations. Since the proposed procedure does not require an SPICE simulation in the synthesis loop, it substantially reduces the design time in circuit design optimization.
  • Thumbnail Image
    ItemOpen Access
    Transaction based verification of DA-FIR filter using AMBA AHBTm transactor
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Lad, Umeshkumar Mangubhai; Dubey, Rahul
    Transaction based verification is used for faster verification purpose. Reusable transactors are designed and designs are verified at transaction level using these transactors. The test bench are written in higher level language and applied to design via Transactor. Hardware emulators accelerate the use of transaction advantages for the verification people. A number of SoCs and components can be verified with this methodology. The Device under test (DUT) used here is 5th order signed DA-FIR filter and the Transactor designed is AMBA® AHB™ from ARM. The Transactor is designed as Bus functional model in Verilog and state machine model in C++. The C++ based test bench gives the command (input) for verifying design. The Transactor takes care of the signal needed for applying to DUT. The tool used for the verification is Eve’s ZeBu. The verification environment and methodology has been described and compared with the present scenario. Complexity and speed performance are the main constraints for the comparison.
  • Thumbnail Image
    ItemOpen Access
    Self-calibrating technique for digital-to-analog converter in successive approximation register analog-to-digital converter
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Patel, Sujit Kumar; Parikh, Chetan D.
    Successive Approximation Register (SAR) analog to digital converter resolution is limited mainly by the capacitor ratio error; comparator offset voltage and capacitor voltage dependence error. A SAR ADC resolution is limited to 10-bit due above errors. Resolution can be increased by using calibration techniques for these errors. From the calibration of capacitor ratio error and comparator offset voltage 16-bit resolution can be achieved. Calibration of capacitor voltage dependence error is necessary for resolution more than 16-bit. This thesis proposes the self calibration technique for capacitor ratio error in differential SAR analog to digital converter. Using this calibration technique capacitor ratio error is minimized. Linear voltage coefficient of capacitor is canceled by the differential SAR ADC but, comparator has limitation of finite common mode rejection ratio (CMRR). In this work self calibration of capacitor voltage dependence error is also discussed in detail.
  • Thumbnail Image
    ItemOpen Access
    Design of the analog front end circuit for X-ray detectors
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Roy, Subhash Chandra; Parikh, Chetan D.
    The Thesis presents a novel idea to efficiently read out the value corresponding to incident X-Ray, from X-Ray sensor. A system level solution has been proposed which is unique in itself in terms of approach. A simple design of analog front end circuit for 64 channels, consisting of Charge Sensitive Preamplifier (CSP), Pulse Shaping Amplifier (PSA), Peak Detector, subtractor, Mux and ADC has been proposed. In CSP, Transmission Gate (TG) has been used, in parallel with integrating capacitor, where the NMOS is operating in weak inversion, when TG is supposed to be off. It fulfils the requirements like posing very high ac resistance, providing alternative path for DC leakage current signal, discharging integrating capacitor quickly etc. An amplifier cum level shifter has been used to match the output DC level of CSP with input DC level of PSA. PSA has been implemented as a 4th order Bessel-Butterworth low pass filter, which provides good step response, and hence output is obtained with negligible peaking. High pass filter hasn’t been used to avoid low frequency signal loss. A subtractor has been proposed after the peak detector, which is taking care of offset voltages and low frequency noise. This system till the output of shaper is providing a resolution of 1.7% against the specification of 3%.
  • Thumbnail Image
    ItemOpen Access
    10-bit high speed high SFDR current steering DAC
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Bapodra, Dhairya B.; Parikh, Chetan D.
    The Thesis presents an attempt to design a 10-bit High Speed High SFDR Current Steering DAC with a simple and different approach. Most of earlier approaches contain complex design and bulky unary portion. Here an approach tried that uses sub-segmentation of unary part. By using sub-segmentation of unary part, reduction in complex decoder block can be introduced. The issue of synchronization is tackle by a latch that is previously proposed for tackling very high frequency. Here by segmentation of unary part area as well as complexity is reduced for decoder. And the sentence that is always true “Simpler Designs are faster”. And reduction in complexity leads to reduction in error sources.
  • Thumbnail Image
    ItemOpen Access
    Low power SRAM design
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Bambhaniya, Prashant; Dubey, Rahul
    In the past, power dissipation was not constraining factor because of device density and operating frequency was low enough. But nowadays due to increased integration and operating frequency of integrated circuits, power consumption has become an important factor. Battery operated portable devices which performing the high performance processing task also consumes lots of power. The various methodologies are used to reduce the power dissipation by optimizing the parameters that are related to power consumption of circuit. The Static RAM is used as a cache memory in the processor and also has an application in the embedded system. Due to continuous advances in the integrated circuit technology, the density of SRAMs in embedded application has grown substantially in recent years. The SRAM block is becoming indispensable block in the system-on-chips (SoCs). The larger density SRAM block has a highly capacitive bit lines and data lines. The dynamic power of SRAM is mainly due to charging and discharging of highly capacitive lines. To perform the write operation in the SRAM cell to flip the data value, nearly full voltage swings is required on the bit line. This full voltage swing on the highly capacitive bit lines will consumes a greater amount power according to law of CV2f. Thus voltage swing reduction is an effective way to decrease the power dissipation. The current mode sensing technique is proposed to give the small voltage swing on the bit lines during write operation. In the proposed method the layout and simulation is done for the one bit line pair for three different methodologies. The bit line interference of selected cell with adjacent selected and non selected cell is also checked out. The proposed current conveyor method has shown an improvement in terms power dissipation over the voltage write and current read (VWCR) and current write and current read (CWCR) method without comprising the performance.
  • Thumbnail Image
    ItemOpen Access
    Design of a high speed I/O buffer
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Rathore, Akhil; Parikh, Chetan D.
    In high speed serial transmission of data, output buffer creates the bottleneck. Current Mode Logic (CML) buffers have gained wide acceptance in most high speed serial interfaces as they reach speed of the order of Gbp/s. CML buffers achieves high speed due to low output voltage swing which reduces transition time. Presently CML buffers are designed with differential architecture and uses different bandwidth extension technique (inductive peaking, negative miller capacitance, active feedback) to increase the speed. At high frequency, input output coupling limits the bandwidth due to miller effect because of gate to drain capacitance. The proposed design incorporates the architecture which reduces miller effect, hence achieves high bandwidth. In this topology a source follower drives a common-gate stage which is an example of ‘unilateral’ amplifier, that is, one in which signal can flow only in one way over large bandwidths. It reduces unintended and undesired feedback. This CML buffer is designed for OC-192/STM-64 application to be used in limiting amplifier which is a critical block in optical system. OC-192/STM-64 works around 10Gbps.
  • Thumbnail Image
    ItemOpen Access
    Design of voltage reference circuits
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Panchal, Bhavi; Parikh, Chetan D.
    Shrinking device dimensions in advancing CMOS technologies require lower supply voltages to ensure device reliability. As a result, analog circuit designers are faced with many challenges in finding new ways to build analog circuits that can operate at lower supply voltages while maintaining performance. Bandgap references are subject to these head-room problems especially when the required supply voltage approaches the bandgap voltage of silicon. However, the bandgap reference working with a low supply voltage often has a higher temperature coefficient than that of a traditional bandgap reference. This has resulted in the development of new temperature-compensated techniques. Piecewise linear curvature correction method is simple yet robust technique which was previously available in bipolar technology. This research work describes a Novel CMOS bandgap reference which uses piecewise-linear curvature compensation scheme for second order correction. In standard 0.18μm CMOS process, the reference, with 1.8 V supply produces an output of about 928 mV, which varies by 160 μV from -25 °C to 150°C. It dissipates 150 μW and has a DC PSRR of -46 dB.
  • Thumbnail Image
    ItemOpen Access
    Design of low power and high speed decoder for 1MB memory
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Gupta, Punam Sen; Nagchoudhuri, Dipankar
    Technology scaling is accompanied by rise in leakage power dissipation. This thesis proposes a voltage controllable circuit in the feedback path of the decoder, which drastically reduces the standby leakage current with minimum loss in speed and slightly overheads in terms of chip area. This circuit generates slightly lower supply voltage when the load circuitry is in the standby mode thereby raises the Vt of the CMOS transistors and hence reduces leakage power dissipation The overall power dissipation of a 7x128 decoder is reduced from 0.928mW to 0.584mW for 1Mb Memory with voltage controllable circuit, namely 37% lowering in power dissipation. The operating voltage for the design is 1.2 V. Layout is done in magic 7.1 version in 180nm technology. The simulations are done in LT spice.
  • Thumbnail Image
    ItemOpen Access
    Design of a CMOS variable gain amplifier
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Verma, Vivek; Parikh, Chetan D.
    In advanced CMOS technologies as device dimensions are decreasing, requirement for lower supply voltages are increasing to make certain device reliability. So, challenges for analog circuit designers are to discover new techniques to design analog circuits that can operate at lower supply voltages with desired performances. Another challenge for designer is to design a circuit with less power consumption while maintaining desired performance. In this thesis, a CMOS variable gain amplifier is designed to target above challenges. A fully differential, CMOS variable gain amplifier (VGA) has been designed for a 1.2- volt, low-power, 57-dB dynamic range, and high bandwidth. The VGA comprises of a control circuit, variable gain stages with common-mode feedback circuit. The gain of the VGA varies dB-linearly from -32 to 25 dB with respect to the control voltage, VC. Proposed VGA uses common-mode feedback (CMFB) circuit to fix and stabilize the output DC levels at a particular voltage depending on the input common-mode range (ICMR) requirement and output swing of the VGA. The proposed VGA uses capacitive neutralization technique to achieve high bandwidth operation. This VGA draws 1.25 mA current from a 1.2 V supply. The 3-dB bandwidth varies from 110 MHZ (at 25 dB gain) to 3828 MHz (at -32 dB gain). The proposed VGA is simulated for 0.18μm CMOS technology in LT-Spice with BSIM3V3 model.