M Tech Dissertations

Permanent URI for this collectionhttp://drsr.daiict.ac.in/handle/123456789/3

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End date: 2009Subject: search.filters.subject.Electronics

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    Statistical co-analysis, robust optimization and diagnosis of USB 2.0 system for signal and power integrity
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Tripathi, Jai Narayan; Dubey, Rahul
    Signal Integrity (SI) and Power Integrity (PI) are the most critical issues as semiconductor industry is moving towards higher operational speeds. Signal integrity and power integrity are such issues that should be looked at system level rather than looking at active and passive networks separately. System level analysis becomes a necessity when the individual subsystems work according to specifications, and even after that complete system doesn't work well. System level signal integrity and power integrity problems for high speed serial links have been taken into account in this thesis. Serial links are being used more and more rather than parallel links due to lesser skew and lower pin counts. Specifically USB 2.0 IP is used for this thesis work, but the analysis is generic for all serial links. This thesis considers SI and PI as a dual and a common model is used which considers both SI and PI. A statistical co-analysis of SI and PI for high speed serial links is used, which can be used for a cost effective solution too. Statistical methods are used for efficient simulations and to extract maximum information contents in the least simulation combinations. Based on this co-analysis, the system is diagnosed or modified for better SI and PI. In the end, reflection gain concept is also taken in to account for the diagnosis of the system. All in all, USB 2.0 system is diagnosed for better SI and PI. System level robustness analysis of high speed serial links are taken into account with effect of external environment. A strong correlation between measured and simulated results is shown. A generic methodology for SI and PI for high speed serial links is presented with complete analysis of package, board, termination, squidd card, decoupling network etc..
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    Design of multi-band fractal antenna for satellite navigation application
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Pathak, Swapna; Gupta, Sanjeev
    Recent efforts by several researchers around the world to combine fractal geometry with electromagnetic theory have led to a plethora of new and innovative antenna designs. This research proposal has been primarily focused in the analysis and design of fractal antenna elements. Fractals have no characteristic size, and are generally composed of many copies of themselves at different scales. These unique properties of fractals will be exploited in order to develop a new class of antenna-element designs that are multi-band and/or compact in size. These key issues are the major motivations for the research project which involves the analysis and design fractal antennas in L, S and C-bands.
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    Design of low power and high speed decoder for 1MB memory
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Gupta, Punam Sen; Nagchoudhuri, Dipankar
    Technology scaling is accompanied by rise in leakage power dissipation. This thesis proposes a voltage controllable circuit in the feedback path of the decoder, which drastically reduces the standby leakage current with minimum loss in speed and slightly overheads in terms of chip area. This circuit generates slightly lower supply voltage when the load circuitry is in the standby mode thereby raises the Vt of the CMOS transistors and hence reduces leakage power dissipation The overall power dissipation of a 7x128 decoder is reduced from 0.928mW to 0.584mW for 1Mb Memory with voltage controllable circuit, namely 37% lowering in power dissipation. The operating voltage for the design is 1.2 V. Layout is done in magic 7.1 version in 180nm technology. The simulations are done in LT spice.
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    Design of a CMOS variable gain amplifier
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Verma, Vivek; Parikh, Chetan D.
    In advanced CMOS technologies as device dimensions are decreasing, requirement for lower supply voltages are increasing to make certain device reliability. So, challenges for analog circuit designers are to discover new techniques to design analog circuits that can operate at lower supply voltages with desired performances. Another challenge for designer is to design a circuit with less power consumption while maintaining desired performance. In this thesis, a CMOS variable gain amplifier is designed to target above challenges. A fully differential, CMOS variable gain amplifier (VGA) has been designed for a 1.2- volt, low-power, 57-dB dynamic range, and high bandwidth. The VGA comprises of a control circuit, variable gain stages with common-mode feedback circuit. The gain of the VGA varies dB-linearly from -32 to 25 dB with respect to the control voltage, VC. Proposed VGA uses common-mode feedback (CMFB) circuit to fix and stabilize the output DC levels at a particular voltage depending on the input common-mode range (ICMR) requirement and output swing of the VGA. The proposed VGA uses capacitive neutralization technique to achieve high bandwidth operation. This VGA draws 1.25 mA current from a 1.2 V supply. The 3-dB bandwidth varies from 110 MHZ (at 25 dB gain) to 3828 MHz (at -32 dB gain). The proposed VGA is simulated for 0.18μm CMOS technology in LT-Spice with BSIM3V3 model.
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    Design of low-voltage, low-power, wide-band CMOS LC VCO using active inductors
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Sesha Sai, Aduru Venkata Raghava; Parikh, Chetan D.
    In this thesis the design of low-voltage, low-power, wide-band CMOS LC VCO using active inductor has been proposed. The oscillator is based upon the classic LC-tuned negative-resistance topology, with a novel active inductor using a low-voltage gyrator topology with a feedback resistance, where feedback resistance is realized by a NMOS operating in triode region whose bias voltage tunes the inductance of the active inductor and hence the frequency of VCO. The simulation results shows that this VCO operates in a 1.19 GHz to 2.49 GHz , while consuming 1.09 mW from a 1.2V power supply. The VCO’s phase noise level is -86.9 dBc/Hz at 1 MHz offset from a 1.55 GHz carrier. The deviation of the phase noise is 11.5 dBc/Hz during this tuning range. All the circuit simulations of VCO were simulated in SpectreRF using TSMC 0.18μm CMOS technology.
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    Design of low voltage high performance voltage controlled oscillator
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Ramesh, R; Nagchoudhuri, Dipankar; Mandal, Sushanta Kumar
    In this thesis an ultra low voltage differential capacitive feedback VCO is being proposed .The VCO operates at very low supply voltage of 0.6V.The VCO uses techniques like Forward Body Bias (FBB), and capacitive feedback to achieve high performance in terms of phase noise and output voltage swing. It uses differential MOS varactors for frequency tuning due to which all low frequency noise such as flicker noise gets rejected. Inductor was designed and it was simulated in IE3D electromagnetic simulator to achieve good Quality factor. This VCO achieves a very low phase noise of -119dBc/Hz@1-MHz offset frequency, power consumption of 3.27mW, and tuning range of 6% .All the circuit simulations of VCO were simulated in SpectreRF using TSMC 0.18μm CMOS technology
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    Symbol detection in MIMO systems
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Dhaka, Kalpana; Chakka, Vijaykumar
    Multiple input multiple output symbol detection methods are observed under frequency flat fading AWGN channel condition. The modulation method employed is Quadrature amplitude modulation (QAM). The various symbol detection techniques are compared to observe their behavior under AWGN channel condition condition. Maximum likelihood (ML) symbol detection method gives the best performance but because of its high complexity it can’t be used. Sphere decoder reduces the complexity to some extent providing similar performance as ML estimate. The other methods used are Zero forcing and Minimum mean square stimation. These two methods when used successively for interference cancellation improves performance to large extent along with reduction in the cost. The technique employed for successive detectionis devised by bell laboratory hence it is called as V-BLAST method. Maximum a posteriori when used along with V-BLAST MMSE algorithm further improves the performance. These methods even works well under Rayleigh channel condition. Finally, the simulation results for performance of V-BLAST under both the channel condition are observed for all the symbol detection techniques. To increase the diversity for improved performance space time trellis code are employed. Their performance is observed for QPSK modulation scheme.
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    CMOS RFIC mixer design
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Gupta, Mukesh; Gupta, Sanjeev
    A CMOS RF (Radio Frequency) up/down conversion mixer results in a reasonable increase in transceiver integration and a reduction in cost. The design of mixers faces many compromises between conversion gain(GC), local oscillator (LO) power, linearity, noise figure (NF), port-to-port isolation, voltage scaling and power consumption. Mixer linearity is a very important parameter in transceiver design, because system linearity is often limited by the first down-conversion mixer due to a relatively large signal compared with that at the LNA input. Since active FET (Field Effect Transistor) mixers achieve conversion gain with lower LO power than their passive counterparts, the active CMOS single-balanced and double-balanced Gilbert mixers are commonly used in the CMOS transceiver design. Compared with the single-balanced counterpart, the double balanced mixer has better port-to- port isolation due to symmetrical architecture. The double-balanced mixer has a higher noise figure due to more noise generators. The overall Gilbert mixer linearity is controlled primarily by the transconductance stage if the LO-driven transistors act as good switches. This report describes a Gilbert cell mixer with source degeneration for 900 MHz frequency. The circuit converts a 900 MHz RF signal directly to base band [IF (Intermediate frequency) 45 MHz] using an 855 MHz LO frequency. The mixer uses common source MOSFETs with inductive degeneration to convert the input RF voltage to a current. This current is then steered using a switching network composed of MOSFETs that is driven with the LO and a 180 degree phase-shifted version of the LO. Gilbert Mixer achieves gain through an active predriver [The V-I (voltage to current) converter]. This V-I converter is highly nonlinear; hence, the Gilbert Mixer distortion performance is worse. This thesis tries to propose a simple linearity improvement technique for Gilbert Cell Mixer by including an additional capacitor located in parallel with the intrinsic gate-source capacitor of the common source transconductance stage. Also, to reduce the flicker noise of the switching transistors which depends on the frequency and circuit capacitance at the common source node of the switching stage, a method is used to reduce this capacitance by adding an extra inductor that helps for simultaneously match low 1/f noise, high linearity and low NF at the expense of Conversion gain. The design is based upon the third order intermodulation distortion (IM3) and output current equations of MOSFETs and flicker noise equation when it is subjected to an ac input signal. The performance has been verified using Agilent’ Advanced Design System (ADS) simulations. The designed mixer has a voltage conversion gain of 15.804 dB, NFSSB of 6.565 dB, NFDSB=3.975 dB, IIP3 of -1.158 dBm, OIP3 USB of 14.699 dBm, OIP3 LSB of 14.646 dBm, LO to IF isolation of -27.532 dB, LO to RF isolation of -69.365 dB and RF to IF isolation of -56.554 dB for single ended RF Input.
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    CMOS latched comparator design for analog to digital converters
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Gupta, Amit Kumar; Parikh, Chetan D.
    Conventional comparators are at the two extremes as far as power delay product and isolation between input and output is concern. Either they achieved very good isolation at the cost of power in the preamplifier or save the static power dissipation in preamplifier in the latching mode which increases the feed through. In this thesis work we propose an optimized CMOS Latch Comparator. The simulation result based on .18um technology, shows the working of the comparator at 500 MHz, with moderate power delay product and isolation compared with the conventional architecture.
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    Frequency compensation technique for low voltage three stage operational amplifier
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Kunde, Raju; Parikh, Chetan D.
    This thesis presents a new frequency compensation technique for low supply voltage three-stage operational amplifier at higher loads. It is based on the miller splitting and pole-zero cancellation using feed-forward path. To reduce the value of compensation capacitance feedback stage is added in series with the compensation capacitance. The amplifier exhibits a dc gain 72db,a gain bandwidth of 35MHz at 63 degree phase margin slew rate 1 v/sμ, a compensation capacitance 4.5pF and load capacitance 300pF while consuming 395Wμat a 1-V supply voltage.