M Tech Dissertations
Permanent URI for this collectionhttp://drsr.daiict.ac.in/handle/123456789/3
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Item Open Access Path planning of data mule using responsible short circuit with steiner points(Dhirubhai Ambani Institute of Information and Communication Technology, 2015) Vora, Ankitkumar; Srivastava, Sanjay; Sunitha, V.We have studied the problem of data aggregation method in wireless sensor network using the data mule. In data mule approach, Data mule is the mobile entity which can collect the data from stationary sensor node in the network. Data mule approach significantly improves the network lifetime. Network lifetime is main concern while designing the application of sensor network because most of the time sensor nodes die due to power discharge. On the other hand Data mule approach increases the data latency compared to other existing methods. There is a trade-off between network lifetime and data latency. Data latency of the data mule can be minimized using the proper motion planning of the data mule. As part of the motion planning we have studied the path selection problem for data mule using the Responsible short circuit algorithm. Responsible short circuit algorithm finds the equivalent responsible edge for two or more consecutive edges of that path. Using the Steiner node placement at the overlap region of sensor node’s communication can further improve the path for the data mule. We have combined the Responsible short circuit algorithm with Steiner node placement and tested using the simulation on java technology. This combination significantly improves the path length compared to existing approaches. We have tested the Responsible short circuit without Steiner node algorithm and Responsible short circuit with Steiner node algorithm for Uniform node deployment as well as the Cluster node deployment. We also have thought about the hybrid approach of Clustering and data mule approach which can improve the path selected for data mule.Item Open Access D-latch based low power memory design(Dhirubhai Ambani Institute of Information and Communication Technology, 2015) Tripathi, Saurabh; Mishra, BiswajitLow power consumption is the main attraction of the digital circuit design in the Sub threshold region of operation. In this region of operation less energy is consumed for active operation and less leakage power is dissipated than higher voltage alternatives. As a trade-off circuits operate slowly because the supply voltage is less than the threshold voltage of the transistors. Sub-threshold operation is considered as an effective solution in designs where low power consumption is the prime concern and operating speed can be sacrificed. The sub-threshold systems need the same voltage level operated memory design. Also, the sub-threshold memory design must be robust in terms of SNM (signal to noise margin) as the operating supply voltage is few hundreds of millivolts depending on technology node. This demands the architecture that ensures the effective data read/write operation under all critical conditions. This research work mainly focuses on D-Latch based 128 Byte full custom memory array and memory controller design. Starting with different latch architectures’ minimum operating supply voltage comparison, the complete Byte addressable memory design flow including row/column decoder design, memory controller design has been discussed. The complete layout of the memory, performance results under an application and its different parameters have also been included in the report. All the design parameters and the simulation results are produced for 0.18μm process.Item Open Access Single electron transistor based 4-bit ALU design, simulation and optimization(Dhirubhai Ambani Institute of Information and Communication Technology, 2015) Joshi, Rathin K.; Parekh, RutuObjective of this thesis work is to create and optimize Single Electron Transistor(SET) based digital design. In present era for electronics, alternative approaches, other than CMOS (like SET,finFET,quantom dot) are much required. This is because of down scaling in MOSFET does not provide efficient results, mainly less than 10 nm feature size. In order to exhibit its applications, SET based digital design of 4-bit multifunctional ALU has been compared with 45 nm CMOS technology. Further using, circuit architecture optimization is performed, which results in significant improvement in design. Entire analysis is done in hierarchical manner: First gate level implementation and its comparison is done, followed by modular performance comparison and finally 4-bit ALU design is compared. So far, no one has done such analysis for design like SET based multifunctional computational tool. Finally, we can conclude that proposed design is energy efficient than 45 nm CMOS or hybrid SET CMOS design. In terms of PDP, SET based optimized design results in 93 % improvment than existing 45 nm CMOS. Transient analysis and PDP analysis have been done in bottom up approach. Low drivabilty and room temeprature operability were the two bottlenecks in SET based design. In this thesis work, design parameters are taken which are appropriate for room temparature, Drivability of SET in increased by modifying circuit architecture. With research advnacement, these two drawbacks have been overcome. In addition to these advantages, all the fabrication parameters are in practically feasible. Hence, proposed design can be fabricated and work at room temprature. SET’s multivalued application has also been verified by considering an example of Qunatizer. Aim behind selecting quantizer is because it is the most basic unit for SET based ADC & DAC circuits. By using only 2 SETs, quantizer is implemented, which is generally bulkier circuit in case of CMOS. This kind of ”Unlike CMOS applications” have few novel benefits with better performance.Item Open Access CTS and CCOpt metodology's to achieve low skew-low power clock.(Dhirubhai Ambani Institute of Information and Communication Technology, 2013) Sreekanth, M.; Bhatt, AmitIn synchronous VLSI chips, clock distribution network plays an important role. The quality of clock network mainly effects the performance of the chip, because the speed of data transfer depends on clock signal. Achieving minimum clock latency and clock skew becomes difficult when we have clock signals in terms of 100MHz. in the clock network, skew is one of the major concerns because of this clock rate decreases. In this document, the main focus is on Clock Tree Synthesis (CTS) methodology for achieving low skew. Primarily CTS requires inputs like target skew, maximum delay, minimum delay. In this report we analyze the effect of these parameters on achieving low skew and low power clock. Then we will try to make a generalized conclusion to get low-skew and low power CTS. Due to on-chip variation, low power and design complexity, clock timing in diverging as technology shrinks down below 45 nm. As transistor goes below 45 nm technology, the timing gap becomes very severe as it reaches up to 50%. Clock Concurrent Optimization is a new approach which merger physical optimization into CTS and optimizes both clock delays and logic delays simultaneously. In this report we will discuss how CCOpt optimizes both logic and clock simultaneously. In addition to that we will discuss the key benefits of CCOpt when compared to CTS.Item Open Access Study of power in CR-SRAM in context of precharge reference voltage.(Dhirubhai Ambani Institute of Information and Communication Technology, 2013) Rupapara, Kripal D.; Zaveri, Mazad SIn Morden times power dissipation in electronic circuits has become more important due to increase use of portable and handheld devices. Increased operating frequency results in more power consumption in almost every VLSI circuits. Scaling in integrated circuit technology directly paves way to increased package density, thereby increasing on chip power. With continuous scaling, low power design techniques results in efficient use of silicon die. Semiconductor memories are most important subsystems of modern digital systems. Modern IC’s allocate 70% of the total chip area to memory design. Large fraction of power is consumed by memory circuits, if we can reduce power consumed by memory structure can reduce overall power consumption. This thesis is mainly concentrated on various components of power consumption in digital circuits, operation of SRAM, various technique to reduce power in SRAM and finally illustrates charge recycling SRAM for lower power consumption.Item Open Access Novel 7T SRAM cell design for low power cache applications(Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Joshi, Srawan Kumar; NagChoudhuri, DipankarScaling in integrated circuit technology directly paves way to increased package density, thereby increasing onchip power. With continuous scaling, low power design techniques results in efficient use of silicon die. Semiconductor memories are most important subsystems of modern digital systems. Modern IC’s allocate 70% of the total chip area to memory design. SRAM is used as on chip cache memory. A major part of the power consumption in any memory architecture is due to charging and discharging of highly capacitive bitlines and wordlines. Existing techniques mainly concentrated on the reduction of power due to the capacitive bitlines and wordlines. In this thesis, a new 7T SRAM cell has been proposed with a single bitline architecture which reduces the dynamic power consumption to a great extent. This proposed design resulted in power reduction of write ‘0’ and read ‘0’ operation, based on the fact that the majority of the cache writes are 0’s. A memory array of size 256Kb (512x512) was designed using the basic 6T SRAM and propsed 7T SRAM cell to carry out the simulations and compare the results for power optimization. The simulations were done using Cadence Virtuoso (ADE) tool in gpdk180 library using 0.18μm technology. With the proposed SRAM cell implementing 256Kb memory array, reduction of write power (approximately 80%) and read power (approximately 55%) is achieved compared to conventional SRAM array. There is an area overhead of 28.76% using the present 180nm technology.Item Open Access Design & layout of a low voltage folding & interpolation ADC for high speed applications(Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Tiwari, Sandeep Kumar; Sen, SubhajitAnalog to Digital Converters (ADC) and Digital to Analog Converters (DAC) plays a vital role in mixed analog signalling, communication and digital signal processing world. Now a day, the demand for designing of high speed, low power and low voltage ADCs are increasing tremendously in high speed data processing applications. In the folding and interpolation ADCs folding amplifiers have the serious bandwidth limitation problem because of larger parasitic capacitance and resistance at the output node. In this thesis work a low voltage and high speed folding and interpolation ADC is implemented using current steering CMOS folding amplifier followed by transresistance amplifier (TRA) in UMC 180nm CMOS technology. The current steering folding amplifier significantly reduces power as well as number of tail current sources compared to the conventional folding amplifier. Transresistance amplifier, which is connected at the output of folding amplifier, avoids the analog bandwidth limitation problem. MSB and LSB bits are generated simultaneously at the output therefore sample and hold circuit is not required in this architecture. This proposed circuit works at 1.8V power supply and 85 MSamples/S and consumes 70mW power. Simulation and Layout of Folding and Interpolation ADC were done using UMC CMOS 180nm technology in the Cadence Analog Design EnvironmentItem Open Access Analysis of charge injection in a MOS analog switch with impedance on source side(Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Rao, D. Srinivas; Sen, SubhajitTurning off of a transistor introduces error voltage at the output of Sample and Hold circuits which are the key components of Analog to Digital Converters (ADCs) and hence limits their accuracy of performance in high switching applications. The error voltage at output is mainly caused because of charge injection due to the carriers released from the channel and due to coupling through gate-to diffusion overlap capacitances. Hence, in order to fully understand the behaviour of charge injection in the presence of source impedance, a device is modelled and simulated in Pisces. This thesis is about modelling of an N-type Metal Oxide Semiconductor (NMOS) device in Pisces Postmini Tool with a hold capacitor on drain side, so that it can be used as a CMOS Analog switch. The main aim is to analyze the trends in output error voltage in the presence of source resistance. The output error caused due to charge injection is examined as a function of different parameters like gate voltage fall time, source resistance, input voltage, substrate concentration etc. Test structures similar to the one modelled in Pisces is simulated in 0.18μm CMOS technology for the verification purpose. It is shown that the modelled and simulated results exhibit good trend agreement.Item Open Access Design of a novel high linearity down conversion mixer for GSM band applications(Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Srinaga, Nikhil N.; Gupta, SanjeevDouble balanced Gilbert cell mixer (GCM) is the mostly used kind of mixer as it provides conversion gain and has port to port isolation. This mixer lacks in linearity and noise figure which are to be taken care in designing mixer. Linearity is important for mixer design, to get an undistorted signal at its output. Similarly noise figure of double balanced GCM is more due to more number of components and is to be decreased to add less noise to RF signal. To increase the linearity of mixer, necessary changes are to be done at transconductance stage. The linearity of the mixer proposed is increased, by making use of an additional capacitor in parallel to gate capacitance and derivative superposition method. Derivative superposition method needs more number of transistors at transconductance stage resulting in increase of parasitic capacitance, resulting in an increase of flicker noise from indirect mechanism. This flicker noise due to parasitic capacitance is reduced by placing a tuned inductor in parallel to itItem Open Access Transaction based verification of multimedia IP(Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Shah, Hirav; Dubey, RahulVerification is major concern in product development life cycle. The number of human hours required writing a test bench and choice of verification approach is the major contributor in the Non Recurring Engineering (NRE) cost. There are too many techniques for verification. Register Transfer level (RTL) verification is too slow. Transaction based verification technique is used for faster verification of any Intellectual Property core. Transaction-based verification allows simulation and debugging at the transaction level, in addition to signal or pin level. All possible transaction types between different modules in a system are created and systematically tested. Design under test (DUT) operates at a binary stimulus level (e.g. Zeros and Ones). Test bench includes one model to define the transactions at a high level and another model to interpret transaction and translates them into the binary level. DUT is implemented in lower abstraction language like Verilog and test bench is created in higher abstraction language like C++. The JPEG Encoder Intellectual Property (IP) core is used as a DUT. This IP is taken from opencores.org website. Whole system is verified on ZeBu emulator.