M Tech Dissertations
Permanent URI for this collectionhttp://drsr.daiict.ac.in/handle/123456789/3
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Item Open Access Self-calibrating technique for digital-to-analog converter in successive approximation register analog-to-digital converter(Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Patel, Sujit Kumar; Parikh, Chetan D.Successive Approximation Register (SAR) analog to digital converter resolution is limited mainly by the capacitor ratio error; comparator offset voltage and capacitor voltage dependence error. A SAR ADC resolution is limited to 10-bit due above errors. Resolution can be increased by using calibration techniques for these errors. From the calibration of capacitor ratio error and comparator offset voltage 16-bit resolution can be achieved. Calibration of capacitor voltage dependence error is necessary for resolution more than 16-bit. This thesis proposes the self calibration technique for capacitor ratio error in differential SAR analog to digital converter. Using this calibration technique capacitor ratio error is minimized. Linear voltage coefficient of capacitor is canceled by the differential SAR ADC but, comparator has limitation of finite common mode rejection ratio (CMRR). In this work self calibration of capacitor voltage dependence error is also discussed in detail.Item Open Access 10-bit high speed high SFDR current steering DAC(Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Bapodra, Dhairya B.; Parikh, Chetan D.The Thesis presents an attempt to design a 10-bit High Speed High SFDR Current Steering DAC with a simple and different approach. Most of earlier approaches contain complex design and bulky unary portion. Here an approach tried that uses sub-segmentation of unary part. By using sub-segmentation of unary part, reduction in complex decoder block can be introduced. The issue of synchronization is tackle by a latch that is previously proposed for tackling very high frequency. Here by segmentation of unary part area as well as complexity is reduced for decoder. And the sentence that is always true “Simpler Designs are faster”. And reduction in complexity leads to reduction in error sources.Item Open Access CMOS latched comparator design for analog to digital converters(Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Gupta, Amit Kumar; Parikh, Chetan D.Conventional comparators are at the two extremes as far as power delay product and isolation between input and output is concern. Either they achieved very good isolation at the cost of power in the preamplifier or save the static power dissipation in preamplifier in the latching mode which increases the feed through. In this thesis work we propose an optimized CMOS Latch Comparator. The simulation result based on .18um technology, shows the working of the comparator at 500 MHz, with moderate power delay product and isolation compared with the conventional architecture.Item Open Access Fault diagnosis algorithm for a flash ADC using oscillation based testing technique(Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Aggarwal, Divya; Parikh, Chetan D.With the advent of system-on-a-chip (SoC) designs, the semiconductor industry wants to solve problems that constrain the coexistence of analog and digital cores on a single chip. The complexities of modern (SoC's), comprising of analog, digital and even Radio-Frequency (RF) blocks on a single chip, are surpassing all the previous limits. Merging so many different technologies poses new challenges, such as developing design and test methodologies capable of ensuring system performance and reliability for a reasonable design effort. Digital testing has developed in to a complete science in the last forty years, but analog and mixed-signal are still in its initial state. The lack of standard models and methodologies is worsening this situation. This work addresses the problem of fault coverage in analog and mixed signal circuits and proposes a fault diagnosis algorithm using Oscillation based Testing Technique. Present calibration techniques compensate for deviations in the measured parameters and do not correct the faulty value, because the faulty value cannot be obtained. A fault diagnosis technique able to perform fault identification (obtain fault values) will lay the groundwork for the development of more effective calibration techniques. Analog to digital converter (ADC) is used as a test vehicle to demonstrate the capability of the proposed OBIST technique. This technique employ Oscillation frequency test data for fault location and identification of the analog components in the converter. In the flash ADC, a fault causes deviation of Oscillation frequency from the ideal one. Hence, it can be considered as a functional signature of the ADC and this property is employed for fault diagnosis. ADC's are virtually in all modern SoC's and hence are one of the most important modules in analog and mixed-signal designs. Here, we have 3-bit, 1 GHz CMOS Flash ADC, designed in 0.18 μm CMOS technology as a benchmark. The simulation results prove that this technique shows an excellent coverage of catastrophic as well as a good coverage of parametric faults, also the algorithm proposed locate the faults in resistive ladder and comparators. The area overhead is very less in this techniques and it works on the circuit speed so, lesser test time.Item Open Access Area reduction in 8 bit binary DAC using current multiplication(Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Upraity, Maitry; Parikh, Chetan D.A proposed current multiplication technique is applied on 8 bit binary current steering Digital-to -Analog Converters with LSB 150 μA, to reduce area. MSB 1 and MSB 2 current are first kept half to reduce area and then current multiplication is performed to get the desired output. Compare to the conventional binary current steering Digital-to-Analog Converters, 20.66% area is reduced and static errors are found within limit. Maximum Integral nonlinearity is-18μA (< LSB) and Differential nonlinearity5.02 μA (< LSB).