M Tech Dissertations

Permanent URI for this collectionhttp://drsr.daiict.ac.in/handle/123456789/3

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    Low noise amplifier design at 2 GHz
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2011) Mavani, Kausha; Gupta, Sanjeev
    Low Noise Amplifier (LNA) is one of the most important building blocks of any wireless receiver. In this an attempt has been made to study two types of LNA designs. The first design is the conventional which consists of the transistor, its biasing network and the input and output matching networks. The second design is an inductorless design which can be further customized to work over a large frequency range. The operating frequency studied in this thesis is 2GHz. A comparison has been made between the two designs and the values of gain and noise figure are satisfactory in both the designs.
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    Asynchronous analog to digital converter
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2011) Patel, Vidyut A.; Parikh, Chetan D.
    Nowadays, asynchronous systems are becoming more popular for low power applications. Asynchronous Systems help to reduce metastability errors and clock skew errors. This thesis is about an asynchronous analog to digital converter (ADC) designed for low power. Here, a design is proposed based on successive approximation algorithm with folding circuit. The folding circuit works as a voltage mapping circuit. The proposed ADC can be used with asynchronous systems as well as conventional synchronous systems. The ADC has been implemented for 5 bit resolution for input voltage range of 0.7V to 2V in 180nm technology. It achieves maximum speed of 8MSPS and DNL of 0.5LSB. The power consumption of the ADC is 2.6mW.
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    Capacitor mismatch in switched capacitor circuits, techniques to minimize mismatch
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2011) Chevella, Subhash; Parikh, Chetan D.
    This thesis about the designing of capacitive mismatch insensitive switched capacitor amplifier for analog to digital converters (ADC). The accuracy of the conversion is an important factor. The accuracy depends upon the residue amplifier used in the designing of the pipelined ADC. So, designing of accurate gain switched capacitor (SC) amplifier is an important concern. The gain accuracy of SC amplifier depends upon the MOS switches, capacitance mismatch and operational amplifier. Among these three, the accuracy will be affected more due to the mismatch of the capacitance values. This thesis is more concentrated on capacitance mismatch. I proposed a switched capacitor amplifier whose gain is less sensitive to capacitance mismatch as compared to conventional switched capacitor amplifier. The percentage of error variation of the gain due to mismatch in proposed circuit varies from 2.1% to 2.9% but in conventional amplifier it varies from -5.1% ~ 8.5%. Proposed circuit has an improvement of 5.6%. All these simulation have done using 180nm technology in LT Spice.
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    Single ended sense amplifier for DRAM
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2011) Aggarwal, Munish; Nagchoudhuri, Dipankar
    Today design of eDRAM is facing more challenges as the technology node is scaling down every year. Supply Voltage is also scaling down in accordance with the technology. Thus, charge on the bitlines, to sense is also decreasing, which is prominent to be affected by noise. Hierarchical based sense amplifier is used to eliminate this effect. This structure reduces the bitline capacitance to 6fF in 90nm technology node. As the ratio of the cell capacitance and the bitline capacitance is increased to 1:10 to 3.3:1 (approx.) which increased the sensing voltage to 600-750mV. Here, sense amplifier can sense the bitline without using the dummy bitlines in the structure i.e., single ended sense amplifier. It eliminates the complex bitline and dummy cell structure from the DRAM array. Cell bitline (Local Bitline LBL) is charged and discharged through the Primary Sense Amplifier (PSA) which is done by utilizing the Secondary Sense Amplifier (SSA). This Secondary Sense Amplifier is connected to the Global Bitline (GBL) through Tertiary Sense Amplifier. Activation of TSA is also not required in the refreshing cycle. Here charge transfer rate from the cell to GBL is also increased by using hierarchical based sense amplifier. Its latency of charge transfer is 1.4ns with typical overall cycle is 2ns. Present hierarchical based amplifier is also cost lower than the other hierarchical based sense amplifiers for eDRAM.
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    Design of the high speed, high accuracy and low power current comparators
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Chasta, Neeraj Kumar; Parikh, Chetan D.
    Comparators are non linear, decision making analog circuits, which find wide spread application in data converters, data transmission and others. Comparison can be done in terms of “Voltage” or “Current”. A current comparator can be referred as trans-impedance amplifiers which compares applied input currents and generate CMOS compatible output voltage. In this work, study and simulations of various current domain comparator circuits have been done; some of these follow basic analog circuit concepts like current mirroring and Voltage current feedback. This thesis presents a novel idea for analog current comparison with controlled hysteresis. Proposed circuit is based on current mirror and latching techniques. Comparator presented is designed optimally in 0.18μm CMOS process in LTspice environment. Designing issues have also been discussed for no hysteresis (or very less hysteresis) case, where comparator gives higher accuracy and speed at the cost of increased power consumption. In addition to this a simple circuit is proposed which satisfies high speed, high accuracy and low power consumption constraints for the mentioned technology parameters. It utilizes amplification properties of Common gate circuit for generating CMOS compatible output voltage by comparison of applied input signal current and reference current
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    Adaptive analog line driver using digital tuning
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Singh, Harsh Verdhan; Sen, Subhajit
    Transmission lines are widely used for transmitting electrical signals. A line driver is a part of the analog front-end transmitter for wired line communication. It is a voltage buffer that provides the necessary output current to drive the small load impedance of a terminated transmission line. The adaptive line driver must adapt to the load impedance of a terminated transmission line for minimizing reflections. The main requirements of an adaptive line driver are good matching to the input impedance of the transmission line over process variations, high output swing, unity gain. Existing adaptive line drivers use analog tuning methods for adapting to the load impedance. This thesis proposes a new technique for tuning output impedance of the line driver. A digital tuning method is used to correct the output impedance of the line driver to match with the input impedance of the transmission line. The aim of using the digital tuning method is to achieve better tuning range over existing analog tuning methods. The tuning scheme uses a comparator followed by counter and current DAC(digital- to-analog converter). A comparator is used for comparing input and output signal of line driver and generates control signal which is applied to a counter that controls the current DAC. This feedback loop ensures unity gain between the input and out- put voltages and thereby ensures tuning of the output impedance of the line driver. The analog line driver is implemented in GPDK-180nm technology and simulated in Cadence Virtuoso Environment.
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    Column decoder for memory redundant cell array
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Nahar, Pinky; Nagchoudhuri, Dipankar
    As the semiconductor technology advances, the yield of memory chip is reducing. The cause of yield degradation is errors in manufacturing process associated with tight geometries. The thesis work proposes a redundancy circuit to enhance the reliability for the faulty columns in memory array. The online testing circuit generates the signals for faulty columns, which enables the redundant circuit to replace faulty with spare column of cells. The redundant decoder and multiplexer provide the path to replace the faulty columns with the spare columns. The novel feature of proposed work is that, input of redundant column decoders depends upon the number of bits for a word output instead of the address signals. The proposed circuit provides the reliability with some loss in speed and overhead in terms of chip area. The operating voltage for the design is 3V. The layout and simulations are performed in CADENCE tool for .1μm technology. The performance parameters of various decoders are performed in LT Spice for .18μm technology.
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    Design of row decoder for redundant memory cell (SRAM)
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Mishra, Ashwini Kumar; Nagchoudhuri, Dipankar
    In the modern technology, the error occurring in memory circuits has increased and the yield of manufacturing has reduced. In order to solve these problems, this thesis proposed a redundancy circuit for faulty row in memory array. The proposed circuit increases the yield and reliability with some loss in speed and overhead in terms of chip area. The circuit designed can test the design whenever a command to test is issued and it will detect and store the faults. Control Circuit designed, checks whether the given address of the memory operation is correct or not. If the address is faulty it replaces the faulty address with the spare address available in the chip. The existing control mechanism to replace faulty cell in a row replaces the cell bit by bit. But the design here instead of replacing the bit wise cells replaces the entire row containing the faulty cell. This architecture is more useful when there are more faulty cells in a single row. The row decoder is optimally implemented to reduce the time to access the data from memory. The operating voltage for the design is 3V. Layout, Simulation of testing circuit and redundant circuit with row decoder has been designed in CADENCE tool for .18μm technology. This Row decoder is working with 2.5GHz frequency.
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    Auto tuning circuit for continuous time filters
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Nadimenti, Rakesh; Sen, Subhajit
    This thesis presents the design of auto tuning circuit for continuous time filters and is designed for applications that require high linearity and moderate precision. This scheme is used to improve tuning range of 50% and obtain an accuracy of 2-7 %. We use discrete capacitor bank to tune RC time constant instead of varying the g m (Tran conductance) to preserve linearity. The auto tuning circuit consists of analog integrator, voltage comparator, capacitor bank, clock generator and a digital tuning engine. By using tuning logic we can generate a control word and set ON chip integrator capacitor to obtain desired RC time constant. The discrete capacitor tuning scheme is designed in 180nm technology to study about the performance of tuning circuit and is simulated in Cadence design environment.
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    High speed sample and hold circuit design
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Dwivedi, Varun Kumar; Parikh, Chetan D.
    Sampling of the time-varying input signal is the first step in any type of Analog to Digital (A/D) conversion. For Low Power and high-speed A/D converter, a high-performance Sample and Hold (S/H) circuit is needed as its front-end component. In this thesis, the high speed sample and hold circuit has been designed, requiring low power as a front end block of pipeline analog to digital converter. In this work, architectures of sample and hold circuit are studied and issues which limit the performance of sample and hold circuits are discussed. A fully differential S/H circuit using bottom plate sampling is proposed. The circuit has been designed in order to meet the specification. Amplifiers are studied and folded-cascode amplifier is chosen as an optimum architecture for switch capacitor based sample and hold circuit. The proposed circuit is designed optimally in a 180 nm CMOS process, in the Cadence Spectre environment. The speed and power achieved are 125 MSPS, 6.8mW respectively.