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Open Access
Extremely low voltage operational amplifier design with rail-to-rail input common mode range
(Dhirubhai Ambani Institute of Information and Communication Technology, 2006) Malviya, Yogesh; Nagchoudhuri, Dipankar
Increasing trends towards battery operated systems demand circuits to be designed at low voltages. Low voltage operation severely limits the operational amplifier as a voltage buffer as the input common mode range available is very limited. This work deals with designing a very low voltage amplifier that can be used as a unity gain buffer. The architecture is based on using an operational amplifier in conjunction with an adapter circuit. The compliance voltage of the tail current source is maintained constant by comparing with a reference voltage using negative feedback action. The amplifier has been designed in 0.18µm technology at a supply voltage of 0.8 Volts. The amplifier gives a constant performance for varying common mode voltage as is demanded for a rail-to-rail amplifier. Designed amplifier gives a gain of 77.4dB with an input stage transconductance ‘Gm’ variation of just 1.29 % over the entire input common mode range.
Open Access
Design of a low power high slew rate OPAMP and to study its impact on sigma delta modulator's performance
(Dhirubhai Ambani Institute of Information and Communication Technology, 2006) Verma, Aseem; Parikh, Chetan D.
This thesis presents the work done on the design of a low-power, high slew rate opamp and subsequently the design of a fully-differential second order Switched-Capacitor architecture of a Sigma Delta modulator in 1.8 V, 0.18 micron CMOS process. A nonsaturated differential input stage is used as an adaptive bias circuit in a Super Class AB opamp, implemented in fully-differential configuration using high swing cascade mirrors. Comparator and clock generating circuit are also designed for the modulator. Various design aspects such as clock feed through, charge injection and KT/C noise have been taken into consideration while designing the modulator. Inaccurate and Incomplete charge transfer in integrator due to bandwidth and slew rate limitations results in gain error and harmonic distortion respectively in the modulator output. Thereby reducing the Signal to Noise and Distortion Ratio of the modulator. Hence Slew rate must be large enough so that the distortion introduced falls below the noise floor of the modulator. Simulation results show that the amplifier has a very small static power dissipation of 0.54 mW, it can supply a maximum output current of 0.65 mA and static power dissipated by sigma delta modulator is 2.7 mW.
Open Access
Low power high speed amplifier design
(Dhirubhai Ambani Institute of Information and Communication Technology, 2006) Bensal, Jitendra Babu; Nagchoudhuri, Dipankar
The operational amplifier (op-amp) is one of the important component in analog to digital converters. The power consumption of these converters mostly depend on the op-amps used. The accuracy and speed performance of analog to digital converters can also be affected due to the finite DC gain and finite bandwidth of the opamp. So the design of op-amp is very critical for these applications. This thesis describes the design of a telescopic operational amplifier. Of the several architectures, a telescopic operational amplifier provides better frequency response and also consumes least power in comparison with other topologies. The limited swing of the telescopic amplifier has been improved by using the current source load transistors in the linear region. Two gain boosting amplifiers are also used to enhance the gain of the amplifier. This gain boosting amplifiers uses a folded - cascode topology. The overall circuit is designed in 0.18 micron CMOS technology at a supply voltage of 1.8 Volt. The operational amplifier achieves a dc gain of 72 dB, bandwidth of 390 MHZ, slew rate of 132 V/ µs and a differential output swing of ± 0.82 V. The overall circuit consumes a total power of 3.36 mw.
Open Access
FM based pipeline ADC
(Dhirubhai Ambani Institute of Information and Communication Technology, 2006) Tandon, Manu; Parikh, Chetan D.
This thesis aims at designing a new architecture for an FM based pipelined Analog to Digital Converter (ADC). It is based on the fact that power is a function of voltage and therefore handling with voltage becomes a difficult task when trying to achieve low power consumption. The idea is to change the very basis on which an ADC works, that is voltage. For frequencies can be generated up to large values without much power consumption. FM based Flash ADCs have been worked upon with power and size reduction for the last decade. An FM based pipelined ADC consists of a mixer and a frequency comparator. The comparator functions by filtering and then converting the signal to a DC value, followed by a digital inverter. The inverter decides the flipping action to zero or one. The mixer is a passive one which generates a subtracted signal with other harmonics as well. As inverter is the only active component and hence this ADC is suitable for low power applications.

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