M Tech Dissertations
Permanent URI for this collectionhttp://drsr.daiict.ac.in/handle/123456789/3
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Item Open Access Asynchronous analog to digital converter(Dhirubhai Ambani Institute of Information and Communication Technology, 2011) Patel, Vidyut A.; Parikh, Chetan D.Nowadays, asynchronous systems are becoming more popular for low power applications. Asynchronous Systems help to reduce metastability errors and clock skew errors. This thesis is about an asynchronous analog to digital converter (ADC) designed for low power. Here, a design is proposed based on successive approximation algorithm with folding circuit. The folding circuit works as a voltage mapping circuit. The proposed ADC can be used with asynchronous systems as well as conventional synchronous systems. The ADC has been implemented for 5 bit resolution for input voltage range of 0.7V to 2V in 180nm technology. It achieves maximum speed of 8MSPS and DNL of 0.5LSB. The power consumption of the ADC is 2.6mW.Item Open Access Capacitor mismatch in switched capacitor circuits, techniques to minimize mismatch(Dhirubhai Ambani Institute of Information and Communication Technology, 2011) Chevella, Subhash; Parikh, Chetan D.This thesis about the designing of capacitive mismatch insensitive switched capacitor amplifier for analog to digital converters (ADC). The accuracy of the conversion is an important factor. The accuracy depends upon the residue amplifier used in the designing of the pipelined ADC. So, designing of accurate gain switched capacitor (SC) amplifier is an important concern. The gain accuracy of SC amplifier depends upon the MOS switches, capacitance mismatch and operational amplifier. Among these three, the accuracy will be affected more due to the mismatch of the capacitance values. This thesis is more concentrated on capacitance mismatch. I proposed a switched capacitor amplifier whose gain is less sensitive to capacitance mismatch as compared to conventional switched capacitor amplifier. The percentage of error variation of the gain due to mismatch in proposed circuit varies from 2.1% to 2.9% but in conventional amplifier it varies from -5.1% ~ 8.5%. Proposed circuit has an improvement of 5.6%. All these simulation have done using 180nm technology in LT Spice.Item Open Access Adaptive analog line driver using digital tuning(Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Singh, Harsh Verdhan; Sen, SubhajitTransmission lines are widely used for transmitting electrical signals. A line driver is a part of the analog front-end transmitter for wired line communication. It is a voltage buffer that provides the necessary output current to drive the small load impedance of a terminated transmission line. The adaptive line driver must adapt to the load impedance of a terminated transmission line for minimizing reflections. The main requirements of an adaptive line driver are good matching to the input impedance of the transmission line over process variations, high output swing, unity gain. Existing adaptive line drivers use analog tuning methods for adapting to the load impedance. This thesis proposes a new technique for tuning output impedance of the line driver. A digital tuning method is used to correct the output impedance of the line driver to match with the input impedance of the transmission line. The aim of using the digital tuning method is to achieve better tuning range over existing analog tuning methods. The tuning scheme uses a comparator followed by counter and current DAC(digital- to-analog converter). A comparator is used for comparing input and output signal of line driver and generates control signal which is applied to a counter that controls the current DAC. This feedback loop ensures unity gain between the input and out- put voltages and thereby ensures tuning of the output impedance of the line driver. The analog line driver is implemented in GPDK-180nm technology and simulated in Cadence Virtuoso Environment.Item Open Access High speed sample and hold circuit design(Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Dwivedi, Varun Kumar; Parikh, Chetan D.Sampling of the time-varying input signal is the first step in any type of Analog to Digital (A/D) conversion. For Low Power and high-speed A/D converter, a high-performance Sample and Hold (S/H) circuit is needed as its front-end component. In this thesis, the high speed sample and hold circuit has been designed, requiring low power as a front end block of pipeline analog to digital converter. In this work, architectures of sample and hold circuit are studied and issues which limit the performance of sample and hold circuits are discussed. A fully differential S/H circuit using bottom plate sampling is proposed. The circuit has been designed in order to meet the specification. Amplifiers are studied and folded-cascode amplifier is chosen as an optimum architecture for switch capacitor based sample and hold circuit. The proposed circuit is designed optimally in a 180 nm CMOS process, in the Cadence Spectre environment. The speed and power achieved are 125 MSPS, 6.8mW respectively.Item Open Access Test methodology for prediction of analog performance parameters(Dhirubhai Ambani Institute of Information and Communication Technology, 2010) Akula, Sandeep; Nagchoudhuri, DipankarAnalog testing, the name itself signifies the detection of faults in analog circuits. The aim of this thesis is to increase the test effectiveness and work in the performance parameter space. There are many test methodologies which can detect the faults in the circuit under test (CUT), out of which the test methodologies which can determine CUT performance parameters resulting in enhanced test effectiveness are, predictive oscillation based test methodologies. To detect the catastrophic and parametric faults these methodologies are used. These test methodologies are preferred over other methodologies because the input test stimulus generation is not needed, which reduces the complexity if multiple inputs are applied to the circuit. These test techniques are implemented with prediction process using neural networks which will in turn increases the performance of the circuit under test. The thesis follows with the implementation of the techniques and understanding the methods to increase the test effectiveness. The design process is performed in CADENCE simulation tool with 180nm technology.Item Open Access FM based pipeline ADC(Dhirubhai Ambani Institute of Information and Communication Technology, 2006) Tandon, Manu; Parikh, Chetan D.This thesis aims at designing a new architecture for an FM based pipelined Analog to Digital Converter (ADC). It is based on the fact that power is a function of voltage and therefore handling with voltage becomes a difficult task when trying to achieve low power consumption. The idea is to change the very basis on which an ADC works, that is voltage. For frequencies can be generated up to large values without much power consumption. FM based Flash ADCs have been worked upon with power and size reduction for the last decade. An FM based pipelined ADC consists of a mixer and a frequency comparator. The comparator functions by filtering and then converting the signal to a DC value, followed by a digital inverter. The inverter decides the flipping action to zero or one. The mixer is a passive one which generates a subtracted signal with other harmonics as well. As inverter is the only active component and hence this ADC is suitable for low power applications.