M Tech Dissertations

Permanent URI for this collectionhttp://drsr.daiict.ac.in/handle/123456789/3

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Subject: search.filters.subject.Analog-to-digital converter

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    All-digital time based analog-to-digital converter and time-to-digital converter
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2015) Sharma, Vineet; Mishra, Biswajit
    The goal of this thesis is to design a fully digital sensor interface. For this, a time-based analog to digital converter and time to digital converter has been investigated. It is concluded that fully digital time-based ADC architecture also yields itself as an TDC with architectural analysis alone. The advantage of the proposed architecture is that it configures the core to function as both ADC and TDC. The resolution of both as TDC as well as ADC and the resolution to be settable. The fully digital circuit has a ring delay line (RDL), latch, encoder and a synchronous counter. The circuit is implemented in 0.18mmdigital CMOS, achieving 139mV/LSB (14-bit, 1-MS/s, 1.6 mW) in ADC mode and 227 ps/LSB (Vin = 1.0 V, 14-bit), 94 ps/LSB (Vin = 1.8 V, 14-bit) in TDC mode respectively.
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    Capacitor mismatch in switched capacitor circuits, techniques to minimize mismatch
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2011) Chevella, Subhash; Parikh, Chetan D.
    This thesis about the designing of capacitive mismatch insensitive switched capacitor amplifier for analog to digital converters (ADC). The accuracy of the conversion is an important factor. The accuracy depends upon the residue amplifier used in the designing of the pipelined ADC. So, designing of accurate gain switched capacitor (SC) amplifier is an important concern. The gain accuracy of SC amplifier depends upon the MOS switches, capacitance mismatch and operational amplifier. Among these three, the accuracy will be affected more due to the mismatch of the capacitance values. This thesis is more concentrated on capacitance mismatch. I proposed a switched capacitor amplifier whose gain is less sensitive to capacitance mismatch as compared to conventional switched capacitor amplifier. The percentage of error variation of the gain due to mismatch in proposed circuit varies from 2.1% to 2.9% but in conventional amplifier it varies from -5.1% ~ 8.5%. Proposed circuit has an improvement of 5.6%. All these simulation have done using 180nm technology in LT Spice.