M Tech Dissertations

Permanent URI for this collectionhttp://drsr.daiict.ac.in/handle/123456789/3

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Subject: search.filters.subject.Analog-to-digital converters

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Now showing 1 - 7 of 7
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    Design & layout of a low voltage folding & interpolation ADC for high speed applications
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Tiwari, Sandeep Kumar; Sen, Subhajit
    Analog to Digital Converters (ADC) and Digital to Analog Converters (DAC) plays a vital role in mixed analog signalling, communication and digital signal processing world. Now a day, the demand for designing of high speed, low power and low voltage ADCs are increasing tremendously in high speed data processing applications. In the folding and interpolation ADCs folding amplifiers have the serious bandwidth limitation problem because of larger parasitic capacitance and resistance at the output node. In this thesis work a low voltage and high speed folding and interpolation ADC is implemented using current steering CMOS folding amplifier followed by transresistance amplifier (TRA) in UMC 180nm CMOS technology. The current steering folding amplifier significantly reduces power as well as number of tail current sources compared to the conventional folding amplifier. Transresistance amplifier, which is connected at the output of folding amplifier, avoids the analog bandwidth limitation problem. MSB and LSB bits are generated simultaneously at the output therefore sample and hold circuit is not required in this architecture. This proposed circuit works at 1.8V power supply and 85 MSamples/S and consumes 70mW power. Simulation and Layout of Folding and Interpolation ADC were done using UMC CMOS 180nm technology in the Cadence Analog Design Environment
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    Analysis of charge injection in a MOS analog switch with impedance on source side
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2012) Rao, D. Srinivas; Sen, Subhajit
    Turning off of a transistor introduces error voltage at the output of Sample and Hold circuits which are the key components of Analog to Digital Converters (ADCs) and hence limits their accuracy of performance in high switching applications. The error voltage at output is mainly caused because of charge injection due to the carriers released from the channel and due to coupling through gate-to diffusion overlap capacitances. Hence, in order to fully understand the behaviour of charge injection in the presence of source impedance, a device is modelled and simulated in Pisces. This thesis is about modelling of an N-type Metal Oxide Semiconductor (NMOS) device in Pisces Postmini Tool with a hold capacitor on drain side, so that it can be used as a CMOS Analog switch. The main aim is to analyze the trends in output error voltage in the presence of source resistance. The output error caused due to charge injection is examined as a function of different parameters like gate voltage fall time, source resistance, input voltage, substrate concentration etc. Test structures similar to the one modelled in Pisces is simulated in 0.18μm CMOS technology for the verification purpose. It is shown that the modelled and simulated results exhibit good trend agreement.
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    6bit 800 MHz time-interleaved analog to digital converter based on successive approximation in 65 nm standard CMOS process
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Salimath, Arunkumar; Nagchoudhuri, Dipankar; Mandal, Sushanta Kumar
    High-speed analog-to-digital converters (ADCs) with resolutions of 6 bits find wide application in instrumentation, wireless systems, optical communication. This dissertation presents a 6 bit, 8 channel Time-Interleaved ADC based on Successive Approximation that performs analog processing only by means of open-loop circuits that are fully differential, thereby achieving a high conversion rate. The work involves the design of a charge redistribution hybrid-DAC, low offset comparator, shift register based phase generator and the SAR Logic. Designed in 65 nm Standard CMOS STMicroelectronics Process, across all the PVT corners, the ADC achieves SNDR of 36 dB and SFDR of 43 dBFS at 800 MHz sampling rate with low input frequencies. When the input frequency is at 300 MHz the SNDR drops to 32.6 dB. The converter draws an average power of 13.5 mW from a 1.2 V supply.
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    CMOS latched comparator design for analog to digital converters
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Gupta, Amit Kumar; Parikh, Chetan D.
    Conventional comparators are at the two extremes as far as power delay product and isolation between input and output is concern. Either they achieved very good isolation at the cost of power in the preamplifier or save the static power dissipation in preamplifier in the latching mode which increases the feed through. In this thesis work we propose an optimized CMOS Latch Comparator. The simulation result based on .18um technology, shows the working of the comparator at 500 MHz, with moderate power delay product and isolation compared with the conventional architecture.
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    Fault diagnosis algorithm for a flash ADC using oscillation based testing technique
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Aggarwal, Divya; Parikh, Chetan D.
    With the advent of system-on-a-chip (SoC) designs, the semiconductor industry wants to solve problems that constrain the coexistence of analog and digital cores on a single chip. The complexities of modern (SoC's), comprising of analog, digital and even Radio-Frequency (RF) blocks on a single chip, are surpassing all the previous limits. Merging so many different technologies poses new challenges, such as developing design and test methodologies capable of ensuring system performance and reliability for a reasonable design effort. Digital testing has developed in to a complete science in the last forty years, but analog and mixed-signal are still in its initial state. The lack of standard models and methodologies is worsening this situation. This work addresses the problem of fault coverage in analog and mixed signal circuits and proposes a fault diagnosis algorithm using Oscillation based Testing Technique. Present calibration techniques compensate for deviations in the measured parameters and do not correct the faulty value, because the faulty value cannot be obtained. A fault diagnosis technique able to perform fault identification (obtain fault values) will lay the groundwork for the development of more effective calibration techniques. Analog to digital converter (ADC) is used as a test vehicle to demonstrate the capability of the proposed OBIST technique. This technique employ Oscillation frequency test data for fault location and identification of the analog components in the converter. In the flash ADC, a fault causes deviation of Oscillation frequency from the ideal one. Hence, it can be considered as a functional signature of the ADC and this property is employed for fault diagnosis. ADC's are virtually in all modern SoC's and hence are one of the most important modules in analog and mixed-signal designs. Here, we have 3-bit, 1 GHz CMOS Flash ADC, designed in 0.18 μm CMOS technology as a benchmark. The simulation results prove that this technique shows an excellent coverage of catastrophic as well as a good coverage of parametric faults, also the algorithm proposed locate the faults in resistive ladder and comparators. The area overhead is very less in this techniques and it works on the circuit speed so, lesser test time.
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    Area reduction in 8 bit binary DAC using current multiplication
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Upraity, Maitry; Parikh, Chetan D.
    A proposed current multiplication technique is applied on 8 bit binary current steering Digital-to -Analog Converters with LSB 150 μA, to reduce area. MSB 1 and MSB 2 current are first kept half to reduce area and then current multiplication is performed to get the desired output. Compare to the conventional binary current steering Digital-to-Analog Converters, 20.66% area is reduced and static errors are found within limit. Maximum Integral nonlinearity is-18μA (< LSB) and Differential nonlinearity5.02 μA (< LSB).
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    Low power high speed amplifier design
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2006) Bensal, Jitendra Babu; Nagchoudhuri, Dipankar
    The operational amplifier (op-amp) is one of the important component in analog to digital converters. The power consumption of these converters mostly depend on the op-amps used. The accuracy and speed performance of analog to digital converters can also be affected due to the finite DC gain and finite bandwidth of the opamp. So the design of op-amp is very critical for these applications. This thesis describes the design of a telescopic operational amplifier. Of the several architectures, a telescopic operational amplifier provides better frequency response and also consumes least power in comparison with other topologies. The limited swing of the telescopic amplifier has been improved by using the current source load transistors in the linear region. Two gain boosting amplifiers are also used to enhance the gain of the amplifier. This gain boosting amplifiers uses a folded - cascode topology. The overall circuit is designed in 0.18 micron CMOS technology at a supply voltage of 1.8 Volt. The operational amplifier achieves a dc gain of 72 dB, bandwidth of 390 MHZ, slew rate of 132 V/ µs and a differential output swing of ± 0.82 V. The overall circuit consumes a total power of 3.36 mw.