M Tech Dissertations

Permanent URI for this collectionhttp://drsr.daiict.ac.in/handle/123456789/3

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Subject: search.filters.subject.Application specific integrated circuits

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    ItemOpen Access
    Analysis of various DFT techniques in the ASIC designs
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2013) Rathod, Gayatri Manohar; Bhatt, Amit
    With the increasing demand of mobile communication industry and highly progressive VLSI technology, muti-million gates silicon chips are in the market. And to have fault free, reliable chips, extended facility of testable circuit has to be added into the original design. The design technique which includes the testability logic into the design at the logical synthesis level is known as Design for Test abbreviated as DFT [1]. To achieve better fault coverage, I have chosen full scan chain insertion technique for OR1200 design. OR1200 is a 32-bit microprocessor with 5-stage pipeline [12]. Its RTL code is taken from opencores.org and Cadence RTL Compiler version 11.1 is used for logic synthesis. For testing and verification, Encounter Test Version 11.1 and NCVerilog simulator is used. To improve the testability of the design, Deterministic fault analysis and Random Resistant Fault Analysis techniques are also added to the design. Effects of all hardware DFT techniques are analysed in terms of area, dynamic power dissipation and gate count. Main low power technique i.e. clock gating is also inserted along with DFT to achieve better performance in terms of power dissipation. DFT causes 25% of increase in die area and 12% of increase in dynamic power. This is acceptable as we will get OR1200 design with 99.67% fault coverage area.
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    ItemOpen Access
    Statistical co-analysis, robust optimization and diagnosis of USB 2.0 system for signal and power integrity
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Tripathi, Jai Narayan; Dubey, Rahul
    Signal Integrity (SI) and Power Integrity (PI) are the most critical issues as semiconductor industry is moving towards higher operational speeds. Signal integrity and power integrity are such issues that should be looked at system level rather than looking at active and passive networks separately. System level analysis becomes a necessity when the individual subsystems work according to specifications, and even after that complete system doesn't work well. System level signal integrity and power integrity problems for high speed serial links have been taken into account in this thesis. Serial links are being used more and more rather than parallel links due to lesser skew and lower pin counts. Specifically USB 2.0 IP is used for this thesis work, but the analysis is generic for all serial links. This thesis considers SI and PI as a dual and a common model is used which considers both SI and PI. A statistical co-analysis of SI and PI for high speed serial links is used, which can be used for a cost effective solution too. Statistical methods are used for efficient simulations and to extract maximum information contents in the least simulation combinations. Based on this co-analysis, the system is diagnosed or modified for better SI and PI. In the end, reflection gain concept is also taken in to account for the diagnosis of the system. All in all, USB 2.0 system is diagnosed for better SI and PI. System level robustness analysis of high speed serial links are taken into account with effect of external environment. A strong correlation between measured and simulated results is shown. A generic methodology for SI and PI for high speed serial links is presented with complete analysis of package, board, termination, squidd card, decoupling network etc..
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    ItemOpen Access
    Analysis and modeling of power distribution network and decoupling network design strategies for high speed digital and analog VLSI system
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2009) Pathak, Abhishek; Mandal, Sushanta; Nagpal, Raj Kumar; Nagchoudhuri, Dipankar
    Today’s high speed digital and analog VLSI systems are operating in GHz frequency range. With high switching rate of the devices, power distribution network (PDN) impedance causes ripples in power supply. If PDN is not designed properly it can cause false switching, or even it can damage the device permanently. In this thesis whole power distribution network (PDN) for VLSI system has been modeled using RLC equivalent circuits which can be run on any simulation program with integrated circuit emphasis (SPICE) based simulator. Frequency dependent RLC model for printed circuit board (PCB) and package interconnects has been generated, and effects of different geometry and material of interconnects on PDN impedance profile have been analyzed. Model is compared with electromagnetic (EM) full wave simulator both for the accuracy and CPU run time and it is found that model shows good accuracy with very less CPU run time as compared to full wave simulator which can take more than a day to simulate whole geometry. To meet the target impedance of PDN, Strategies for choosing decoupling capacitors and their placement over power plane have been analyzed. Key-words: Power Integrity, power delivery network, voltage regulator, simultaneous switching noise.
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    ItemOpen Access
    Low power SRAM design
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2008) Bambhaniya, Prashant; Dubey, Rahul
    In the past, power dissipation was not constraining factor because of device density and operating frequency was low enough. But nowadays due to increased integration and operating frequency of integrated circuits, power consumption has become an important factor. Battery operated portable devices which performing the high performance processing task also consumes lots of power. The various methodologies are used to reduce the power dissipation by optimizing the parameters that are related to power consumption of circuit. The Static RAM is used as a cache memory in the processor and also has an application in the embedded system. Due to continuous advances in the integrated circuit technology, the density of SRAMs in embedded application has grown substantially in recent years. The SRAM block is becoming indispensable block in the system-on-chips (SoCs). The larger density SRAM block has a highly capacitive bit lines and data lines. The dynamic power of SRAM is mainly due to charging and discharging of highly capacitive lines. To perform the write operation in the SRAM cell to flip the data value, nearly full voltage swings is required on the bit line. This full voltage swing on the highly capacitive bit lines will consumes a greater amount power according to law of CV2f. Thus voltage swing reduction is an effective way to decrease the power dissipation. The current mode sensing technique is proposed to give the small voltage swing on the bit lines during write operation. In the proposed method the layout and simulation is done for the one bit line pair for three different methodologies. The bit line interference of selected cell with adjacent selected and non selected cell is also checked out. The proposed current conveyor method has shown an improvement in terms power dissipation over the voltage write and current read (VWCR) and current write and current read (CWCR) method without comprising the performance.
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    ItemOpen Access
    ASIC implementation of discrete fourier transform processing module
    (Dhirubhai Ambani Institute of Information and Communication Technology, 2007) Gupta, Navneet; Dubey, Rahul
    This work presents the design and ASIC implementation of Discrete Fourier Transform Processing Module. The performance of designed DFT processing module is better than radix-2 and radix-4 FFT algorithms, and is comparable to Split radix FFT algorithm, in terms of computational requirements. Different architectures are proposed for DFT processing module, and their comparative analysis is done. ASIC implementation of Discrete Fourier Transform processing module includes, its modelling using Verilog HDL, gate level synthesis of the modelled design and physical synthesis of netlist generated by gate level synthesis. The functionality of Design after physical synthesis is verified. Designed DFT processing module is retargetable and can be used as an IP.